1. ELE22MIC Lecture 19, 20, 21 Edge Detector Latch vs Flip Flop
S-R Latch, Transparent D-Latch
Clocked D-Latch
J-K Flip Flop, Toggle Flip Flop
Flip Flop Applications
Register/Memory, Shift Register, Counter
68HC11 Analog to Digital Converter
Variable Speed Stepper Motor Application

3. 68HC11 Timer - PreScaler
Crystal Frequency vs clock Pre-Scaler

4. Edge Detection
Positive-Going Edge Detection

5. Clocked Set Reset Latch

6. Transparent D Latch

7. Edge Triggered D Flip Flop
Positive Clock Edge-Triggered
D Flip Flop

8. J-K Flip Flop

9. J-K Flip Flop

10. Toggle Flip Flop
While the toggle pin is held high, the Q line changes state on every positive CLK transition.

11. 4 Bit - Ripple Counter

12. Timer-Counter Pre-Scaler

13. 3 Bit Shift Register

14. Variable Speed Stepper Motor
The next application we will look at is a Variable Speed Stepper Motor control
The forward/reverse speed is controlled by a potentiometer connected to the ADC input

15. Variable Speed Stepper Motor
The unsigned potentiometer value is biased by 128 so that mid-way = 0 speed, 255 = full speed forwards, -255 = full speed reverse.
The stepper motor coil activation sequence is controlled by four output lines of Port A

16. ULN2003

17. Stepper Motor

18. ULN2003

19. Variable Speed Stepper Motor (1)
REGBAS EQU $ Starting address for register block
RAM EQU $2000
PORTA EQU $ Port A INPUT:PA0..2, OUTPUT:PA3..6, & I/O PA7
* Port Outputs can be used when not using timer
* latches specified in TCTL1 (below)
PORTB EQU $ Output port B
CFORC EQU $0B Force Output Compare...
OC1M EQU $0C OClM7,OClM6,OClM5,OClM4;OClM3,-,-,-
OC1D EQU $0D OClD7,OClD6,OClD5,OClD4;OClD3,-,-,-
TCNT EQU $0E Free running counter (16 bit)
TIC1 EQU $ IC1 register (16 bit)
TOC1 EQU $ OC1 register (16 bit)
TOC2 EQU $ OC2 register (16 bit)
TOC3 EQU $1A OC3 register (16 bit)

20. Variable Speed Stepper Motor (2)
TCTL1 EQU $ OM2,OL2,OM3,OL3;OM4,OL4,OM5,OL5
TCTL2 EQU $ ,-,EDGlB,EDGlA;EDG2B,EDG2A,EDG3B,EDG3A
TMSK1 EQU $ OC1I,OC2I,OC3I,OC4I;OC51,IC1I,IC2I,IC3I
TFLG1 EQU $ OC1F,OC2F,OC3F,OC4F;OC5F,IC1F,IC2F,IC3F
TMSK2 EQU $ TOI,RTII,PAOVI,PAII;-,-,PR1,PR0
TFLG2 EQU $ TOF,RTIF,PAOVF,PAIF;-,-,-,-
PACTL EQU $ DDRA7:PAEN:PAMOD:PEDGE:-:-:RTR1:RTR0
* DDRA7 - Data Direction Register for Port A bit 7
* PAEN - Pulse Accumulator ENable
* PAMOD - For Pulse Accumulator - See Section 11 of ref.man.
* PAMOD = 0 -> Event Count,
* PAMOD= 1 -> Gated Time Accumulation
* RTR1:RTR0 - Select Real Time Interrupt Rate

21. Variable Speed Stepper Motor (3)
*** HC-COM Routine Addresses & Pseudo Vector Equates
.OUTA EQU $FFB Print character in A-reg
.OUTCRL EQU $FFC Output <cr><lf>
.OUTSTO EQU $FFCA Output Msg seg (no <cr,lf>)
.OUTSTR EQU $FFC Output Msg w/leading <cr,lf>
PVIC1 EQU $00E EVB Pseudo Vector for IC1
PVTOF EQU $00D EVB Pseudo Vector for TOF
PVOC2 EQU $00DC EVB Pseudo Vector for OC2
PVOC1 EQU $00DF EVB Pseudo Vector for OC1
REGS EQU $ * 68HC11 Config Registers base location
TOF EQU % * Timer overflow flag
N EQU * times for one sec

22. Variable Speed Stepper Motor (4)
OPTION EQU $39
ADCTL EQU $30
ADR1 EQU $31
ADSET EQU % * A/D input on PE-4
CCF EQU % * Conversion complete flag
ADPU EQU % * A/D power up bit
* * * Monitor Equates
OUTLHF EQU $FFB2 Print left half
OUTRHF EQU $FFB5 Print right half
CRLF EQU $FFC4 Print CRLF

23. Variable Speed Stepper Motor (5)
*** RAM Variable Assignments
ORG RAM Start variables in EVB RAM (upper half)
JMP START
HDLY RMB Half-cycle delay (in 0.5mS increments)
* Some routines use only first 5 bytes of DBUFR
ADCVAL RMB 1
StepDirn RMB 2
StepPtr RMB 2 * Pointer to items in following table
StepTable FCB % , % , FCB % , % ,
StepEnd EQU *

24. Variable Speed Stepper Motor (6)
START:
TOP5 LDS #$ * Top of User's Stack area on EVB
LDD #$0
STD StepDirn
LDD #$8000
STD HDLY
LDAA #$7E * Jump (extended) Opcode
STAA PVOC * Pseudo Vector see manual text
LDX #SV5OC * Address of OC2 service routine
STX PVOC * Finish jump instruc to TOF svc

25. Variable Speed Stepper Motor (7)
LDX #REGBAS * Point to 68HC11 configuration register block
LDAA #% *
STAA OC1M, X * Output Compare Mask = 0 for all OCs
LDAA #% * OM2:OL2 = 0:1
STAA TCTL1,X * SET All timers not connected to outputs
LDAA #% * OM2:OL2 = 0:1
STAA TFLG1,X * Clear any pending,OC2F
STAA TMSK1,X * Enable OC2 interrupts
CLI * Enable Interrupts
LDX #StepTable
STX StepPtr * StepPtr -> Start of stepper table values

26. Variable Speed Stepper Motor (8)
LDX StepPtr * Get our table pointer -> X
LDAA 0, X * Get the contents of the table -> Acc A
LDX #REGBAS * Get configuration register base address -> X
STAA PORTA, X * Store initial Stepper motor position
LDAA #%
STAA OC1D, X
STAA CFORC, X
BSET OPTION,x ADPU * Power up the ADC *
JSR delay100us * Wait for Charge Pump to stabilise

27. Variable Speed Stepper Motor (9)
* Start the conversion SCAN=0, MULT=0
FOREVER:
* Beginning of LOOP-FOREVER
LDAA #ADSET * Select ADC input from Port E-4
STAA ADCTL,x * Signal ADC to start conversion
* Wait until conversion done
convwait:
BRCLR ADCTL,x CCF convwait
* Get the input and print it using the BUFFALO Monitor
LDAA ADR1, x * Get ADC converted input voltage value

28. Variable Speed Stepper Motor(10)
PSHA
SUBA #$80
STAA ADCVAL * Store for ISR use
BPL PlusOne
BMI MinusOne
LDD #0
BRA StorDirn * If 0, store 0
PlusOne:
LDD #1
BRA StorDirn
MinusOne:
NEGA * A = -A
LDD #-1

29. Variable Speed Stepper Motor(11)
StorDirn:
STD StepDirn
LDAA ADCVAL
SUBA #$7F
NEGA
ASLA
LDAB #0
STD HDLY * Speed - save delay
PULA
TAB * save it (A) in B
JSR OUTLHF * output high nybble
TBA * restore it to A
JSR OUTRHF * output low nybble
JSR CRLF * output carriage return - line feed

30. Variable Speed Stepper Motor(12)
* Clear the TOF to start the delay
JSR delay100us
BRA FOREVER * loop forever

31. Variable Speed Stepper Motor(13)
***
* SV5OC2 - Output Compare 2 service routine
* Called at each OC2 interrupt.
SV5OC2:
LDD HDLY * Get delay time for 1/2 cycle
LDX #REGBAS
ADDD TOC2,X * Add HDLY to last compare value
STD TOC2,X * Update OC2 (schedule next edge)
BCLR TFLG1,X $BF * Clear OC2F
LDD StepPtr * X = Table Pointer
ADDD StepDirn * 1, 0 or -1
XGDX

32. Variable Speed Stepper Motor(14)
CPX #StepEnd * If at end of table, then wrap to start
BLT NoWrap
LDX #StepTable * by Re-Loading the starting address of table
BRA StorePtr
NoWrap:
CPX #StepTable * If before start of table, then wrap back to end
BGE NoWrapBack
LDX #StepEnd * by Loading the ending address of table
NoWrapBack:
StorePtr:
STX StepPtr * Save next address
LDAA 0, X * A = Next Stepper Value

33. Variable Speed Stepper Motor(15)
* LDX #REGBAS
STAA REGBAS+PORTA * activate next stepper coil
RTI ** Return from OC2 service **

34. Variable Speed Stepper Motor(16)*
* This subroutine delays (a little over) 100 micro-seconds
delay100us:
PSHA * save Accumulator A
* * Generate a "short" delay > 100 microsec
LDAA #40 * 40 loops for 200 clock cycles at 0.5 micro seconds/clock
DELAYLOOP:
DECA *
BNE DELAYLOOP
PULA * restore Accumulator A
RTS *

35. Analog to Digital Converter
Analog to Digital Converter section of 68HC11
Requires 32 E-clock cycles to complete a conversion
8-bit successive approximation converter.
Uses Charge re-distribution for manufacturability reasons.
As it is based upon capacitance it automatically includes Sample & Hold functionality

36. Analog to Digital Converter
Analog switches are used to provide ADC internal capacitor switching and input multiplexor selection switching.
Uses internal charge pump -> 7 to 8V
Provides high gate voltages to operate analog switches - guarantees low impedance.
must be enabled (disabled at reset)
A/D Power Up (ADPU) control bit
after starting charge pump, must delay 100us before using ADC

37. Analog to Digital Converter
Uses clock sources - must be selected
Four channels are converted in sequence with the results provided in registers

38. ADC - Input Sample VX In the sample phase of the conversion:
VX, the input voltage, is used to charge the bottom plate of the capacitors relative to the VL low reference (top plate).

39. ADC - Sample
Time is allowed to elapse for 12 cycles, sufficient time for VC, the voltage on the capacitors, to charge to VX - VL.
Working with ratios of capacitances.
Total Charge is Q = = 16 units.
The Charge Q = 16 (VX - VL). Setting VL =0 volts => Q = 16 VX.

40. ADC - Hold In the hold phase of the conversion:
The charge remains on the capacitors, and the capacitors bottom plate (reference) is shifted to VL.
QH = - 16 Vi (assuming VL =0). Now Vi = - (VX - VL).

41. ADC - Conversion (1)

42. ADC - Conversion (2)
In the Successive Approximation phase of the conversion:
The voltage on the capacitors, is re-distributed between the 1 unit capacitor, and the VH reference voltage.
The ratio of capacitance determines Vi = (VH/VL) CSEL/C1.
The resulting comparator input voltage is set reflects the input
Resistive losses and timing are ignored to simplify analysis.

43. ADC - Conversion (3)
Starting with the 8 unit capacitor (MSB), it is switched VH.
The charge is Q = 8 (VH - Vi) + 8 (VL - Vi).
Q = 8VH - 16Vi assuming Vi = 0.
The ratio of capacitance determines Vi = (VH/VL) CSAR/C1.
The resulting comparator input voltage is set reflects the input ratio.
If the VX < 8/16 (VH - VL) then Vi > VL and the comparator will output a 1. C8 is set to VH, and a 1 is saved in the MSB of the Successive Approximation register (SAR).
Conversely if VX > 8/16 (VH - VL) then the comparator will output a 0. C8 is set to VL, And a 0 is saved in the MSB of the Successive Approximation register.

44. ADC - Conversion (4)
Next the 4 unit capacitor (MSB), the capacitor is switched VH.
The resulting comparator input voltage is set reflects the input ratio.
And the SAR will save the value of the next most significant bit.
The ADC continues through the rest of the bits until all capacitors have been set and the SAR holds the value of the conversion.
Upon conversion completion:
VX = (VH - VL) x (SAR / 256)

45. ADC - OPTION register
Setting the ADPU bit = 1 turns on the on-chip charge pump.
The CSEL Control Bit selects which charge pump is activated:
0 - ADC (highest ADC accuracy)
1 - EEPROM (needed for EEPROM efficiency)

46. ADC - ADCTL register
The ATCTL Control Register Specifies Channel Assignments
The CCF flag is set to 1 upon completion of 4 conversions, so we can wait for conversion complete using the BRCLR instruction.
If the SCAN bit = 1, continuous conversions occur and the CCF bit is always 1.
CCF can only be read. Bits 0..5 are read/write.

47. ADC - SCAN bit SCAN - Continuous Scan Control
If SCAN=0, four conversions are performed, filling the four result registers.
If SCAN=1, then the A-D conversion continues in a round-robin fashion, and the result registers are updated (but the CCF bit remains set).
CD = 0, CC=0 -> AN0..AN3 in ADR1..ADR4
CD=0, CC = 1 -> AN4..AN7 in ARD1..ADR4

48. ADC - MULT bit MULT - Multiple Channel Control
If the MULT bit=0, then a single channel is converted and the result stored.
If MULT=1, then a conversion is performed on each channel in a group of 4 channels

49. ADC - Channel Assignments

50. ADRx - AD Result Registers
The ADRx Results registers receive the converted level from the ADC.
ADR1 - $1031
ADR2 - $1032
ADR3 - $1033
ADR4 - $1034

51. ADC Code (1) REGS EQU $1000 ; Registers
TOF EQU % ; Timer overflow flag
N1 EQU ; times for one sec
TFLG2 EQU $25
OPTION EQU $39
ADCTL EQU $30
ADR1 EQU $31
ADSET EQU % ; A/D input on PE-4
CCF EQU %
; Conversion complete flag
ADPU EQU % ; A/D power up bit

52. ADC Code (2) ; Monitor Equates OUTLHF EQU $FFB2 Print left half
OUTRHF EQU $FFB5 Print right half
CRLF EQU $FFC4 Print CRLF
; Memory Map Equates
CODE EQU $2000
DATA EQU $7000
STACK EQU $05F
ORG CODE
LDS #STACK
LDX #REGS

53. ADC Code (3) ; Power up the A/D charge pump. BSET OPTION,x ADPU
; Generate a "short" delay > 100 microsec
LDAA #40 ; 40 loops for 200 clock cycles
DELAY
DECA
BNE DELAY
; Start the conversion SCAN=0, MULT=0
LOOP:
LDAA #ADSET
STAA ADCTL,x

54. ADC Code (4) ; Wait until conversion done spin: BRCLR ADCTL,x CCF spin
; Get the input and print it using the BUFFALO Monitor
LDAA ADR1, x
TAB ; save it
JSR OUTLHF
TBA ; restore it
JSR OUTRHF
JSR CRLF

55. ADC Code (5) ; Delay approx 1 second using the timer overflow
LDAB #N ; Clear the TOF to start the delay
delay1 :
ldaa #TOF
staa TFLG2,x
; and wait for N1 overflows
spin1:
TST TFLG2,x
BPL spin1
DECB
BNE delay1
BRA loop

56. Acknowledgments
Images of the configuration registers, and some source code examples, are derived from the Motorola M68HC11 Reference Manual