1. (Sequential Logic Circuit)
Computer Engineering
(Logic Circuits)
Lec. # 11
(Sequential Logic Circuit)
Dr. Tamer Samy Gaafar
Dept. of Computer & Systems Engineering
Faculty of Engineering
Zagazig University

2. Course Web Page http://www.tsgaafar.faculty.zu.edu.eg

3. Flip-Flop Excitation Tables
Present State
Next State
F.F.
Input
Q(t)
Q(t+1) D 1
Present State
Next State
F.F.
Input
Q(t)
Q(t+1) J K 1
0 0 (No change)
0 1 (Reset) 1
0 x
1 x
x 1
x 0
1 0 (Set)
1 1 (Toggle)
0 1 (Reset)
1 1 (Toggle)
0 0 (No change)
1 0 (Set)
Present State
Next State
F.F.
Input
Q(t)
Q(t+1) S R x 1
Q(t)
Q(t+1) T 1 1

4. Copyright 2009 - Joanne DeGroat, ECE, OSU
Mealy and Moore
Sequential machines are typically classified as either a Mealy machine or a Moore machine implementation.
Moore machine: The outputs of the circuit depend only upon the current state of the circuit.
Mealy machine: The outputs of the circuit depend upon both the current state of the circuit and the inputs.
Copyright Joanne DeGroat, ECE, OSU
9/15/09 - L22 Sequential Circuit Design

5. Mealy and Moore Models Mealy Moore Present State I/P Next State O/P AB x y 1
Present State
I/P
Next State
O/P A B x y 1
For the same state, the output changes with the input
For the same state, the output does not change with the input

6. Moore State Diagram State / Output 1 0 0 / 0 0 1 / 0 1 1 1 1 / 11
0 0 / 0
0 1 / 0 1 1
1 1 / 1
1 0 / 0 1

7. Sequential Circuit Design
Design procedure:
Start with circuit specifications – description of circuit behavior.
Derive the state table.
Perform state reduction if necessary.
Perform state assignment.
Determine number of flip-flops and label them.
Choose the type of flip-flop to be used.
Derive circuit excitation and output tables from the state table.
Derive circuit output functions and flip-flop input functions.
Draw the logic diagram.

8. Design: Example #1
Given the following state diagram, design the sequential circuit using JK flip-flops. 00 10 11 1 01

9. Design: Example #1
Circuit state/excitation table, using JK flip-flops. 00 10 11 1 01
JK Flip-flop’s
excitation table.
0 X
0 X
1 X
X 1
X 0
0 X
1 X
0 X
X 0
X 0
X 0
X 1

10. Design: Example #1 Block diagram. J Q Q' K What are to go in here?
Combinational
circuit A' A B B' x KA JA KB JB B’ A’
External
input(s) CP
output(s)
(none) J Q Q' K
What are to go in here?

11. Design: Example #1 From state table, get flip-flop input functions. A1 x Bx X
JA = B.x'
KA = B.x A B 1 x Bx X
JB = x A B 1 x Bx X
KB = (A  x)' A B 1 x Bx X

12. Design: Example #1 Flip-flop input functions. JA = B.x' JB = x
KA = B.x KB = (A  x)'
Logic diagram: x B A CP J Q Q' K

13. Design: Example #2
Design, using D flip-flops, the circuit based on the state table below. CS

14. Design: Example #2
Determine expressions for flip-flop inputs and the circuit output y. A B 1 x Bx
DA = A.B' + B.x' A B 1 x Bx
DB = A'.x + B'.x + A.B.x' A B 1 x Bx
DA(A, B, x) = S m(2,4,5,6)
DB(A, B, x) = S m(1,3,5,6)
y(A, B, x) = S m(1,5)
y = B'.x

15. Design: Example #2 From derived expressions, draw logic diagram: D Q
DA = A.B' + B.x'
DB = A'.x + B'.x + A.B.x'
y = B'.x D Q Q' A A' B B' y CP x

16. Design: Example #3 Design with unused states. Given these Derive theseCS

17. Design: Example #3
From state table, obtain expressions for flip-flop inputs. A C 00 01 11 10 x AB Cx 1 B X A C 00 01 11 10 x AB Cx 1 B X
SA = B.x
RA = C.x' B A C 00 01 11 10 x AB Cx 1 X A C 00 01 11 10 x AB Cx B X 1
RB = B.C + B.x'
SB = A'.B'.x CS

18. Design: Example #3
From state table, obtain expressions for flip-flop inputs (cont’d). A C 00 01 11 10 x AB Cx 1 B X A C 00 01 11 10 x AB Cx 1 B X
SC = x'
RC = x B A C 00 01 11 10 x AB Cx 1 X
y = A.x CS

19. Design: Example #3 From derived expressions, draw logic diagram: A A'
SA = B.x SB = A'.B'.x SC = x'
RA = C.x' RB = B.C + B.x' RC = x
y = A.x A A' B B' y CP x S Q Q' R C
Design: Example #3 CS

20. Design of Synchronous Counters
Counter: a sequential circuit that cycles through a sequence of states.
Binary counter: follows the binary sequence. An n-bit binary counter (with n flip-flops) counts from 0 to 2n-1.
Example 1: A 3-bit binary counter (using T flip-flops).
001
000
111
010
011
100
110
101
Design of Synchronous Counters CS

21. Design of Synchronous Counters
3-bit binary counter (cont’d). A2 A1 A0 1 A2 A1 A0 1 A2 A1 A0 1
TA2 = A1.A0
TA1 = A0
TA0 = 1
Design of Synchronous Counters CS

22. Design of Synchronous Counters
3-bit binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1 1 A2 CP T Q A1 A0
Design of Synchronous Counters CS

23. Design of Synchronous Counters
Example 2: Counter with non-binary sequence:
000  001  010  100  101  110 and back to 000
001
000
010
100
110
101
JA = B JB = C JC = B'
KA = B KB = 1 KC = 1
Design of Synchronous Counters CS

24. Design of Synchronous Counters
Counter with non-binary sequence (cont’d).
JA = B JB = C JC = B'
KA = B KB = 1 KC = 1 CP A 1 J Q Q' K B C
001
000
010
100
110
101
111
011
Design of Synchronous Counters CS

25. Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s 1
S0 / 0
S1 / 0
State
A B S0
0 0 S1
0 1 S2
1 0 S3
1 1 1
S3 / 1
S2 / 0 1 1

26. Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Output A B x y 1
S0 / 0
S1 / 0
S3 / 1
S2 / 0 1

27. Design of Clocked Sequential Circuits
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Output A B x y 1
Synthesis using D Flip-Flops
A(t+1) = DA (A, B, x)
= ∑ (3, 5, 7)
B(t+1) = DB (A, B, x)
= ∑ (1, 5, 7)
y (A, B, x) = ∑ (6, 7)

28. Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops B 1 A x
DA (A, B, x) = ∑ (3, 5, 7)
= A x + B x
DB (A, B, x) = ∑ (1, 5, 7)
= A x + B’ x
y (A, B, x) = ∑ (6, 7)
= A B B 1 A x B A 1 x

29. Design of Clocked Sequential Circuits with D F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using D Flip-Flops
DA = A x + B x
DB = A x + B’ x
y = A B

30. Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
Flip-Flop
Inputs A B x JA KA JB KB 1
Synthesis using JK F.F.
JA (A, B, x) = ∑ (3)
KA (A, B, x) = ∑ (4, 6)
JB (A, B, x) = ∑ (1, 5)
KB (A, B, x) = ∑ (2, 3, 6)
0 x
1 x
x 1
x 0
0 x
1 x
x 1
x 0

31. Design of Clocked Sequential Circuits with JK F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using JK Flip-Flops
JA = B x KA = x’
JB = x KB = A’ + x’ B 1 A x B x A 1 B 1 x A B x 1 A

32. Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1’s
Present State
Input
Next State
F.F. A B x
TA TB 1
Synthesis using T Flip-Flops 1 1
TA (A, B, x) = ∑ (3, 4, 6)
TB (A, B, x) = ∑ (1, 2, 3, 5, 6)

33. Design of Clocked Sequential Circuits with T F.F.
Example:
Detect 3 or more consecutive 1’s
Synthesis using T Flip-Flops
TA = A x’ + A’ B x
TB = A’ B + B  x B 1 A x B 1 A x