1. CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 8: Synchronous Sequential Circuits Chapter 8

2. Synchronous Sequential Circuits Sequential circuits – outputs depend on past behavior as well as present inputs. Synchronous circuits – use a clock signal to sequence behavior. Asynchronous circuits – no clock signal is used (see Chapter 9).

3. Figure 8.1 The general form of a sequential circuit Combinational circuit Flip-flops Clock Q W Z Combinational circuit

4. Circuit has one input, w, and one output, z. Changes occur on positive clock edge. z is 1 if w is 1 during last two clock cycles. Figure 8.2 Sequences of input and output signals Clockcycle: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w:01011011101 z:00000100110 A Simple Example

5. Figure 8.3 State diagram of a simple sequential circuit Cz1=  Reset Bz0=  Az0=  w0= w1= w1= w0= w0= w1=

6. Figure 8.4 State table Present Next state Output state w=0w=1 z AAB0 BAC0 CAC1

7. Figure 8.5 A general sequential circuit Combinational circuit Combinational circuit Clock y 2 z w y 1 Y 1 Y 2

8. Figure 8.6 A State-assigned table Present Next state state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A 00 01 0 B 0010 0 C 0010 1 11dd d

9. Figure 8.7 Derivation of logic expressions w 00011110 0 1 0 10 y 2 y 1 Y 1 wy 1 y 2 = w 00011110 0 1 0d 1d y 2 y 1 Y 2 wy 1 y 2 1 y 2 += d d 0 0 0 0 0 0 1 01 0 1 0 d y 1 zy 1 y 2 = 0 1 y 2 Y 1 1 y 2 = Y 2 1 2 += zy 2 = wy 1 y 2 + () = Ignoring don't caresUsing don't cares

10. Figure 8.8 Sequential circuit

11. Figure 8.9 Timing diagram t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0 1 0 1 0 1 0 Clock w y 1 y 2 1 0 z

12. Summary of Design Steps Obtain specification of the desired circuit. Create a state diagram from specification. Create a state table from state diagram. Perform state minimization. Perform state assignment. Derive the next-state logic expressions. Implement circuit described by logic.

13. Figure 7.56 A digital system with k registers R1 in Rk in Bus Clock R1 out R2 in R2 out Rk out Control circuit Function R1R2Rk Data Extern

14. Figure 7.58 A shift-register control circuit D Q Q Clock D Q Q D Q Q w R2 out R3 in  Reset R1 out R2 in  R3 out R1 in 

15. Figure 8.10 Signals needed in Example 8.1 Control circuit w Clock Done R1 out R2 R1 in R2 R3 out R3 in

16. Figure 8.11 State diagram DR3 out 1=R1 in 1=Done1=  w0= w1= CR1 out 1=R2 in 1=  BR2 out 1=R3 in 1=  w1= ANo  w0= w1= transfer w0= w1= Reset w0=

17. Figure 8.12 State table Present Next stateOutputs state AAB0000000 BCC0010010 CDD1001000 DAA0100101 w = 0w = 1

18. Figure 8.13 State-assigned table

19. Figure 8.14 Derivation of next-state expressions

20. Figure 8.15 Sequential circuit

21. Figure 8.16 Improved state assignment Present Next state statew=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z A00 010 B 00110 C 00111 10dd d 1

22. Figure 8.17 Final circuit for the improved state assignment D Q Q D Q Q Y 2 Y 1 w Clock z y 1 y 2 Resetn

23. Figure 8.18 Improved state assignment

24. Figure 8.19 Derivation of next-state expressions w 00011110 0 1 1 11 y 2 y 1 Y 1 wy 2 y 1 y 2 += w 00011110 0 1 11 11 y 2 y 1 Y 2 y 1 =

25. Figure 8.20 One-hot state assignment Present Nextstate state w=0w=1 Output y 3 y 2 y 1 Y 3 Y 2 Y 1 Y 3 Y 2 Y 1 z A001 0100 B 0011000 C 0011001 1

26. Figure 8.21 One-hot state assignment

27. Figure 8.22 Sequences of input and output signals Clock cycle:t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 w :01011011101 z :00001001100 1 Mealy State Model Moore machines – output is determined only be present state. Mealy machines – output depends on both present state and input values.

28. Figure 8.23 State diagram A w0=z0=  w1=z1=  B w0=z0=  Reset w1=z0=  Present Next stateOutput z state w=0w=1w=0w=1 AAB00 BAB01

29. Figure 8.24 State table Present Next stateOutput z state w=0w=1w=0w=1 AAB00 BAB01 Present Next stateOutput state w=0w=1w=0w=1 yYYzz A00100 B10101

30. Figure 8.26 FSM implementation Clock Resetn D Q Q w z (a) Circuit t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0 1 0 1 0 1 0 Clock y w z y (b) Timing diagram

31. Figure 8.27 FSM implementation

32. Figure 8.28 State diagram for Example 8.4 R 3 out 1= R 1 in 1= Done 1=  w 0= w 1= R 1 out 1= R 2 in 1=  w 1= R  2 out 1= R 3 in 1=  A w 0= w 1= Reset w 0= B C

33. Figure 7.59 A modified control circuit D Q Q Clock D Q Q D Q Q w R2 out R3 in  R1 out R2 in  R3 out R1 in  P Reset

34. Design of FSMs using CAD tools Could design using manual techniques then use schematic capture or structural VHDL. Instead should enter state table via a state diagram editor or behavioral VHDL.

35. Figure 8.29a VHDL code for a simple FSM USE ieee.std_logic_1164.all ; ENTITY simple IS PORT (Clock, Resetn, w : IN STD_LOGIC ; z: OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN con’t...

36. CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; Figure 8.29b VHDL code for a simple FSM (con’t)

37. Figure 8.30 Implementation of an FSM in a CPLD

38. Figure 8.31 An FSM circuit in a small CPLD

39. Figure 8.32 Simulation results (a) Timing simulation results (b) Magnified simulation results, showing timing details

40. (ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; Figure 8.33a Alternative style of code for an FSM

41. WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; Figure 8.33b Alternative style of code for an FSM (con’t)

42. (ENTITY declaration not shown) ARCHITECTURE Behavior OF simple IS TYPE State_TYPE IS (A, B, C) ; ATTRIBUTE ENUM_ENCODING : STRING ; ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ; SIGNAL y_present, y_next : State_type ; BEGIN con’t... Figure 8.34 A user-defined attribute for manual state assignment

43. Figure 8.35a Using constants for manual state assignment LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( Clock, Resetn, w : INSTD_LOGIC ; z: OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0); CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ; CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ; CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; … con’t

44. Figure 8.35b Using constants for manual state assignment (cont’) WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; WHEN OTHERS => y_next <= A ; END CASE ; END PROCESS ; PROCESS ( Clock, Resetn ) BEGIN IF Resetn = '0' THEN y_present <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ;

45. Figure 8.36 VHDL code for a Mealy machine LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mealy IS PORT ( Clock, Resetn, w : IN STD_LOGIC ; z: OUT STD_LOGIC ) ; END mealy ; ARCHITECTURE Behavior OF mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; … con’t

46. Figure 8.36b VHDL code for a Mealy machine (con’t) WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; END IF ; END PROCESS ; PROCESS ( y, w ) BEGIN CASE y IS WHEN A => z <= '0' ; WHEN B => z <= w ; END CASE ; END PROCESS ; END Behavior ;

47. Figure 8.37 Simulation results for the Mealy machine

48. Figure 8.38 Potential problem with asynchronous inputs to a Mealy FSM

49. Figure 8.39 Block diagram of a serial adder SumAB += Shift register Adder FSM Shift register B A a b s Clock

50. Figure 8.40 State diagram for the serial adder

51. Figure 8.41 State table for the serial adder Present Next stateOutput s state ab =0001101100011011 GGGGH0110 HGHHH1001 Present Next stateOutput state ab =0001101100011011 y Ys 000010110 101111001

52. Figure 8.43 Circuit for the adder FSM Full adder a b s D Q Q carry-out Clock Reset Yy

53. Figure 8.44 State diagram for the Moore-type serial adder FSM H 1 s1=  Reset H 0 s0=  01 10 11 01 10 G 1 s1=  G 0 s0=  01 10 00 01 00 10 11 00 11

54. Figure 8.45 State table for the Moore-type serial adder FSM Present Nextstate Output state ab=00011011s G 0 G 0 G 1 G 1 H 0 0 G 1 G 0 G 1 G 1 H 0 1 H 0 G 1 H 0 H 0 H 1 0 H 1 G 1 H 0 H 0 H 1 1 Present Nextstate state ab =00011011 Output y 2 y 1 Y 2 Y 1 s 00000101100 0100 01101 01 10110 011010111

55. Figure 8.47 Circuit for the Moore-type serial adder FSM Full adder a b D Q Q Carry-out Clock Reset D Q Q s Y 2 Y 1 Sum bit y 2 y 1

56. Figure 8.48a Code for a left-to-right shift register with an enable input LIBRARY ieee ; USE ieee.std_logic_1164.all ; -- left-to-right shift register with parallel load and enable ENTITY shiftrne IS GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w: IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftrne ; ARCHITECTURE Behavior OF shiftrne IS BEGIN PROCESS BEGIN … con’t

57. WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF E = '1' THEN IF L = '1' THEN Q <= R ; ELSE Genbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ; Q(N-1) <= w ; END IF ; END PROCESS ; END Behavior ; Figure 8.48b Code for a left-to-right shift register with an enable input (con’t)

58. Figure 8.49a VHDL code for the serial adder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY serial IS GENERIC ( length : INTEGER := 8 ) ; PORT (Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) ); END serial ; ARCHITECTURE Behavior OF serial IS COMPONENT shiftrne GENERIC ( N : INTEGER := 4 ) ; PORT (R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; SIGNAL s, Low, High, Run : STD_LOGIC ; SIGNAL Count : INTEGER RANGE 0 TO length ; TYPE State_type IS (G, H) ; SIGNAL y : State_type ; … con’t

59. Figure 8.49b VHDL code for the serial adder (con’t) BEGIN Low <= '0' ; High <= '1' ; ShiftA: shiftrneGENERIC MAP (N => length) PORT MAP ( A, Reset, High, Low, Clock, QA ) ; ShiftB: shiftrne GENERIC MAP (N => length) PORT MAP ( B, Reset, High, Low, Clock, QB ) ; AdderFSM: PROCESS ( Reset, Clock ) BEGIN IF Reset = '1' THEN y <= G ; ELSIF Clock'EVENT AND Clock = '1' THEN CASE y IS WHEN G => IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ; ELSE y <= G ; END IF ; WHEN H => IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ; ELSE y <= H ; END IF ; END CASE ; END IF ; END PROCESS AdderFSM ; … con’t

60. Figure 8.49c VHDL code for the serial adder (con’t) WITH y SELECT s <=QA(0) XOR QB(0) WHEN G, NOT ( QA(0) XOR QB(0) ) WHEN H ; Null_in '0') ; ShiftSum: shiftrne GENERIC MAP ( N => length ) PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ; Stop: PROCESS BEGIN WAIT UNTIL (Clock'EVENT AND Clock = '1') ; IF Reset = '1' THEN Count <= length ; ELSIF Run = '1' THEN Count <= Count -1 ; END IF ; END PROCESS ; Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum END Behavior ;

61. Figure 8.50a Synthesized serial adder Adder FSM Clock E w L E w L b 7 b 0 a 7 a 0 E w L E L Q 3 Q 2 Q 1 Q 0 D 3 D 2 D 1 D 0 1000 Counter 00 Reset Sum 7 0 0 1 0 1 Run

62. Figure 8.50b Simulation results for the synthesized serial adder

63. State Minimization It is often difficult for designer to find FSM with minimal number of states. Fewer states leads to fewer flip-flops. Two states S i and S j are equivalent iff for every input sequence starting in S i or S j, the same output sequence is produced.

64. Partitioning Minimization If w=0 in S i and result is S u then S u is 0-successor. If w=1 in S i and result is S v then S v is 1-successor. S i and S j are equivalent if k-successors equivalent. Consider states as set then break set into partitions comprised of subsets which are not equivalent. A partition consists of 1 or more blocks, each block comprises a subset of states that may be equivalent, but states in a block are definitely not equivalent to states in another block.

65. Figure 8.51 State table for Example 8.5 Present Next state Output state w=0w=1 z ABC1 BDF1 CFE0 DBG1 EFC0 FED0 GFG0

66. Figure 8.52 Minimized state table for Example 8.5 Present Nextstate Output state w=0w=1 z ABC1 BAF1 CFC0 FCA0

67. Figure 8.53 Signals for the vending machine D Q Q sense N D Q Q Clock N sense N D Clock N D (a) Timing diagram (b) Circuit that generates N

68. Figure 8.54 State diagram for Example 8.6 S10  S71  DN DN S30  S60  S91  S81  S20  S51  S41  DN D DN DN N Reset

69. Figure 8.55 State table for Example 8.6

70. Figure 8.56 Minimized state table for Example 8.6 Present Next state Output state DN=00011011 z S1 S3S20 S4S50 S3 S2S40 S11 S5S31 – – – ––– –––

71. Figure 8.57 Minimized state diagram for Example 8.6 S10  S51  DN D D D N N N S30  S2  0 S41 

72. Figure 8.58 Mealy-type FSM for Example 8.6 S3 S2 D0  S1 D1  D1  N1  N0  N0  DN0  0  0 

73. Incompletely Specified FSMs Partitioning scheme works well when all entries in state table are specified. If one or more entries are not specified, then the FSM is incompletely specified. Partitioning scheme not guaranteed to produce minimal solution in this case.

74. Figure 8.59 Incompletely specified state table for Example 8.7 Present Next stateOutput z state w=0w=1w=0w=1 ABC00 BD0 CFE01 DBG00 EFC01 FED01 GF0 – – – –

75. Figure 8.59 Incompletely specified state table for Example 8.7 Present Next stateOutput z state w=0w=1w=0w=1 ABC00 BD0 CFE01 DBG00 EFC01 FED01 GF0 – – – –

76. Figure 8.60 State diagram for a counter w 0= w 1= w 0= w 1= w 0= w 1= w 0= w 1= w 0= w 1= w 0= w 1= w 0= w 1= w 0= w 1= A/0B/1C/2D/3 E/4F/5G/6H/7

77. Figure 8.61 State table for the counter Present Next state Output state w=0w=1 AAB0 BBC1 CCD2 DDE3 EEF4 FFG5 GGH6 HHA7

78. Figure 8.62 State-assigned table for the counter Present Next state statew=0w=1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0 A000 001000 B001 010001 C010 011010 D011 100011 E100 101100 F101 110101 G110 111110 H111 000111

79. Figure 8.63 Karnaugh maps for D flip-flops for the counter 00011110 00 01 1 01 1 1 0 0 0 0 10 0 0 1 1 111 10 y 1 y 0 wy 2 00011110 00 01 0 00 1 1 1 1 0 1 01 0 0 1 1 011 10 y 1 y 0 wy 2 00011110 00 01 0 11 0 1 0 1 0 1 00 0 1 1 0 111 10 y 1 y 0 wy 2 Y 2 2 y 0 y 2 y 1 y 2 w+++y 0 y 1 y 2 = Y 0 0 0 +=Y 1 1 y 1 y 0 0 y 1 ++=

80. Figure 8.64 Circuit diagram for the counter

81. Implementation Using JK-FF If FF in state 0 to remain 0, J=0 and K=d. If FF in state 0 to change to 1, J=1 and K=d. If FF in state 1 to remain 1, J=d and K=0. If FF in state 1 to change to 0, J=d and K=1.

82. Figure 8.65 Excitation table for the counter with JK flip-flops Present Flip-flop inputs state w=0w=1 Count y 2 y 1 y 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 Y 2 Y 1 Y 0 J 2 K 2 J 1 K 1 J 0 K 0 z 2 z 1 z 0 A 000 0d 0010d 1d000 B 001 0d d00100d1dd1001 C 010 0dd00d0110dd01d010 D 011 0dd0 1001dd1 011 E 100 d00d 101d00d1d100 F 101 d00dd0110d01dd1101 G 110 d0 0d111d0 1d110 H 111 d0 000d1 111

83. Figure 8.66 Circuit diagram for the counter 00011110 00 01 0 00 d d d d 0 1 01 d d d d 011 10 y 1 y 0 wy 2 J 1 0 = 00011110 00 01 d 0d d d 0 0 0 d 1d d d 1 1 111 10 y 1 y 0 wy 2 J 0 w = 00011110 00 01 0 d0 0 0 d d d 1 d1 1 1 d d d11 10 y 1 y 0 wy 2 00011110 00 01 d dd 0 0 0 0 d d dd 1 1 0 0 d11 10 y 1 y 0 wy 2 K 1 0 = K 0 w = 00011110 00 01 0 dd 0 d 0 d 0 d 00 d 1 d 0 d11 10 y 1 y 0 wy 2 J 2 0 y 1 = 00011110 00 01 d 00 d 0 d 0 d 0 dd 1 d 0 d 011 10 y 1 y 0 wy 2 K 2 0 y 1 =

84. Figure 8.67 Circuit diagram using JK flip-flops

85. Figure 8.68 Factored-form implementation of the counter

86. Figure 8.69 State table for the counterlike example PresentNextOutput state z 2 z 1 z 0 AB000 BC100 CD010 DE110 EF001 FG101 GH011 HA111

87. Figure 8.70 State-assigned table PresentNextOutput state y 2 y 1 y 0 Y 2 Y 1 Y 0 z 2 z 1 z 0 0001000 100010100 0101100 110001110 0011010 101011101 0111110 111000111

88. Figure 8.71 Circuit for the counterlike example D Q Q z 0 D Q Q D Q Q z 1 z 2 w

89. Figure 8.72 State diagram for the arbiter Idle 000 1xx Reset gnt1g 1  1= x1x gnt2g 2  1= xx1 gnt3g 3  1= 0xx1xx 01xx0x 001xx0

90. Figure 8.73 Alternative style of state diagram for the arbiter r 1 r 2 r 1 r 2 r 3 Idle Reset gnt1g 1  1= gnt2g 2  1= gnt3g 3  1= r 1 r 1 r 1 r 2 r 3 r 2 r 3 r 1 r 2 r 3

91. Figure 8.74a VHDL code for the arbiter LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY arbiter IS PORT ( Clock, Resetn : IN STD_LOGIC ; r : IN STD_LOGIC_VECTOR(1 TO 3) ; g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ; END arbiter ; ARCHITECTURE Behavior OF arbiter IS TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ; SIGNAL y : State_type ; BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN y <= Idle ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE y IS WHEN Idle => IF r(1) = '1' THEN y <= gnt1 ; ELSIF r(2) = '1' THEN y <= gnt2 ; ELSIF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ; … con’t

92. Figure 8.74b VHDL code for the arbiter (con’t) WHEN gnt1 => IF r(1) = '1' THEN y <= gnt1 ; ELSE y <= Idle ; END IF ; WHEN gnt2 => IF r(2) = '1' THEN y <= gnt2 ; ELSE y <= Idle ; END IF ; WHEN gnt3 => IF r(3) = '1' THEN y <= gnt3 ; ELSE y <= Idle ; END IF ; END CASE ; END IF ; END PROCESS ; g(1) <= '1' WHEN y = gnt1 ELSE '0' ; g(2) <= '1' WHEN y = gnt2 ELSE '0' ; g(3) <= '1' WHEN y = gnt3 ELSE '0' ; END Behavior ;

93. Figure 8.75 Incorrect VHDL code for the grant signals. PROCESS( y ) BEGIN IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ; END Behavior ;

94. Figure 8.76 Correct VHDL code for the grant signals. PROCESS( y ) BEGIN g(1) <= '0' ; g(2) <= '0' ; g(3) <= '0' ; IF y = gnt1 THEN g(1) <= '1' ; ELSIF y = gnt2 THEN g(2) <= '1' ; ELSIF y = gnt3 THEN g(3) <= '1' ; END IF ; END PROCESS ; END Behavior ;

95. Figure 8.77 Simulation results for the arbiter circuit

96. Figure 8.78 Output delays in the arbiter circuit a) Output delays using binary encoding b) Output delays using one-hot encoding

97. Figure 8.80 Circuit for Example 8.8

98. Figure 8.81 Tables for the circuit in Example 8.8 Present Next State state w=0w=1 Output y 2 y 1 Y 2 Y 1 Y 2 Y 1 z 0000010 0100100 1000110 1100 1 (a)State-assigned table Present Next state Output state w=0w=1 z AAB0 BAC0 CAD0 DAD1 (b)State table

99. Figure 8.82 Circuit for Example 8.9 J Q Q Clock Resetn y 2 y 1 J 2 J 1 w z K J Q Q K K 2 K 1

100. Figure 8.83 Excitation table Present Flip-flop inputs statew=0w=1 Output y 2 y 1 J 2 K 2 J 1 K 1 J 2 K 2 J 1 K 1 z 00010100110 0110110 10010100100 11010110101

101. Figure 8.84 Circuit for Example 8.10

102. Figure 8.85 Excitation table Present Flip-flop inputs state w=0w=1 Output y 2 y 1 T 2 D 1 T 2 D 1 z 0000010 0100100 1010010 1110 1

103. Figure 8.86 Elements used in ASM charts Output signals or actions (Moore type) State name Condition expression 0 (False) 1 (True) Conditional outputs or actions (Mealy type) (a) State box(b) Decision box (c) Conditional output box

104. Figure 8.87 ASM chart for a simple FSM w w w 01 0 1 0 1 A B C z Reset

105. Figure 8.88 ASM chart for the FSM in Figure 8.23

106. Figure 8.89 ASM chart for the arbiter r1 r3 0 1 1 Idle Reset r2 r1 r3 r2 gnt1 gnt2 gnt3 1 1 1 0 0 0 g1 g2 g3 0 0 1

107. Figure 8.90 The general model for a sequential circuit Combinational circuit Y k Y 1 y k y 1 w 1 w n z 1 z m Outputs Next-state variables Present-state variables Inputs

108. Formal Model for FSMs M = (W, Z, S, , ) –W is finite, nonempty set of inputs. –Z is finite, nonempty set of outputs. –S is finite, nonempty set of states. –  is the state transition function: S(t+1) =  [W(t),S(t)] – is the output function: (t) = [S(t)] (Moore model) (t) = [W(t),S(t)] (Mealy model)

109. Summary FSM Design (Moore and Mealy) –State minimization –State assignment –Using CAD tools and VHDL