1. Synchronous Circuit Design (Class 10.1 – 10/30/2012) CSE 2441 – Introduction to Digital Logic Fall 2012 Instructor – Bill Carroll, Professor of CSE

2. Today’s Topics Design of synchronous sequential circuits Lab 8 prelab design exercise

3. Introduction to Synchronous Circuit Design (Synthesis) Given the circuit requirements (specifications), i.e., word description, state diagram, state table, etc. Find a hardware realization of the circuit.

4. Introductory Design Example (from example 8.6, figure 8.21) Given the following state diagram and state table. Derive a circuit realization. Assume D flip-flops will be used for memory. State DiagramState Table

5. Generate the Transition Table State Table State Assignment Transition Table (Binary state table) (How many flip-flops are needed?)

6. Produce the Logic Equations Transition Table (Binary state table) Output K-mapFlip-flop Excitation (input) K-maps z = xy 1 ’y 2 + x’y 1 y 2 ’D 1 = y 1 y 2 ’ + xy 2 D 2 = x’y 1 + xy 1 ’

7. Realize the Logic Equations with Gates and Flip-flops z = xy 1 ’y 2 + x’y 1 y 2 ’ D 1 = y 1 y 2 ’ + xy 2 D 2 = x’y 1 + xy 1 ’

8. Lab 8 Preview Analyze, design and implement finite state machines (FSM) – Prelab 1.Use Quartus/Qsim to analyze a given synchronous circuit (FSM A) 2.Design a realization of a second circuit (FSM B) given it’s state diagram. 3.Use Quartus/Qsim to verify the design from 2 is correct. – In lab 1.Construct and test FSM A on the IDL 800 2.Construct and test FSM B on the DE1

9. Test Your Understanding (Lab 8, Prelab 2) Design a realization of the following state diagram. Use D flip flops as memory.

10. Test Your Understanding – Self-Check Given the state diagram. x z1z2z1z2 01 AB00 CB01 DB11 AB10 Construct a state table. A B C D y1y2y1y2 x z1z2z1z2 01 00 0100 011101 11100111 10000110 Y1Y2Y1Y2 Construct a Transition/Output Table Construct Excitation Table For D flip-flops, transition tables and excitation tables are the same with D 1 =Y 1 and D 2 = Y 2.

11. Test Your Understanding – Self-Check Construct Excitation MapsGenerate logic equations for D 1, D 2, z 1, and z 2 y1y2y1y2 x 01 0000 0110 1110 1000 y1y2y1y2 x 01 0001 0111 1101 1001 D1D1 D2D2 D 1 = x’y 2 D 2 = x + y 1 ’y 2 z 1 = y 1 z 2 = y 2

12. Test Your Understanding – Self-Check Realize the logic equations with gates and flip flops

13. Using JK Flip Flops as Memory for Figure 8.2 (Example 8.7) Figure 8.23 J 1 = xy 2 K 1 = x’y 2 J 2 = xy 1 ’ + x’y 1 K 2 = xy 1 + x’y 1 ’

14. Clocked JK Flip-Flop Implementation (Example 8.7) Figure 8.24 J 1 = xy 2 K 1 = x’y 2 J 2 = xy 1 ’ + x’y 1 K 2 = xy 1 + x’y 1 ’

15. Test Your Understanding Design a realization of the following state diagram. Use JK flip flops as memory.

16. Test Your Understanding – Self-Check Given the state diagram. x z1z2z1z2 01 AB00 CB01 DB11 AB10 Construct a state table. A B C D y1y2y1y2 x z1z2z1z2 01 00 0100 011101 11100111 10000110 Y1Y2Y1Y2 Construct a Transition/Output Table Construct Excitation Tables y1y2y1y2 x 01 000d 011d0d 11d0d1 10d1 y1y2y1y2 x 01 000d1d 01d0 11d1d0 100d1d J1K1J1K1 J2K2J2K2

17. Test Your Understanding – Self-Check Construct Excitation MapsGenerate logic equations for J 1, K 1, J 2, K 2, z 1, and z 2 y1y2y1y2 x 01 0000 0110 11dd 10dd y1y2y1y2 x 01 0001 01dd 11dd 1001 J1J1 J2J2 J 1 = x’y 2 K 1 = x + y 2 ’ J 2 = x K 2 = x’y 1 z 1 = y 1 z 2 = y 2 y1y2y1y2 x 01 00dd 01dd 1101 1011 y1y2y1y2 x 01 00dd 0100 1110 10dd K1K1 K2K2

18. Test Your Understanding – Self-Check Realize the logic equations with gates and flip flops

19. Synchronous Circuit Design (Synthesis) Step 1 – Given a description (specification) of the circuit requirements, derive a state table that meets the requirements. Often it’s easier to first derive a state diagram followed by the equivalent state table. Step 2 – Find a state table with a minimum number of states that is equivalent to the original state diagram. Step 3 – Choose a state assignment and generate the state and output transition tables. Step 4 – Determine (select) the memory device or flip-flop type to be used and find the flip-flop excitation maps. Step 5 – From the excitation maps, produce (derive) logic equations for the flip-flop inputs. Also, form output maps and produce (derive) the output logic equations. Step 6 – Draw the logic circuit using the logic equations and appropriate logic devices (gates and flip-flops).