1. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 1 Digital Systems Design Shyue-Kung Lu Department of Electronic Engineering

2. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 2 Syllabus Recommended Texts 1. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL,” Prentice Hall ( 新月圖書 ) References 1. Richard S. Sandige, “Digital Design Essentials,” Prentice Hall ( 開發圖書 ) 2. John F. Wakerly, “Digital Design: Principle and Practices,” Prentice Hall ( 新月圖書 ) 3. M. Morris Mano, “Digital Design,” Prentice Hall, Third Edition ( 滄海書 局， 04-27088787) 4. M. Morris Mano, :Digital Logic and Computer Design Fundamentals,” Prentice Hall ( 新月圖書 ) Grades 1. 作業 25% 2. 期中考 30 % 3. 期末考 30% 4. Project 15% Project 以歷屆 FPGA 比賽題目為主

3. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 3 Digital Systems Design Course Overview Review of combinational and sequential logic design Introduction to synthesis with HDLs (Verilog HDL) Programmable logic devices (CPLD and FPGA) State machines, datapath controllers, RISC CPU Architectures and algorithms for computation Synchronization across clock domains Static Timing Analysis Fault simulation and testing, JTAG, BIST

4. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 4 Chapter 1-3 Review of Digital Systems

5. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 5 Logic Level Ranges of Voltage for a Digital Circuit

6. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 6 Representations of a Digital Design + b a out Z = A' B' (C + D) = (A' (B' (C + D))) True table Logic expression Gate netlist Transistor circuit

7. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 7 Basic Primitives

8. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 8 Some Common IC Gates

9. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 9 Typical IC Datasheet

10. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 10 Combinational Logic Circuit  Combinational circuit: logic circuit whose outputs at any time are determined directly and only from the present input combination.  A combinational circuit performs a specific information- processing operation fully specified logically by a set of Boolean functions.  Sequential circuit: one that employ memory elements in addition to (combinational) logic gates—their outputs are determined from the present input combination as well as the state of the memory cells.

11. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 11 Block Diagram of a Combinational Circuit Combinational Circuit n inputsm outputs Fig. 4-1: Block Diagram of Combinational Circuit

12. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 12 Combinational Modules  Ripple Carry Adder  Carry Look ahead Adder  Binary Adder-Subtractor  BCD Adder  Magnitude Comparator  Binary Multiplier  Decoder/Encoder  Priority Encoder  Multiplexers/Demultiplexers  Three-State Gates

13. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 13 Sequential Circuits

14. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 14 Synchronous Clocked Sequential Circuit

15. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 15 Clock Response in Latch and Flip-Flop

16. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 16 Setup time and Hold Time

17. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 17 DFF

18. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 18 JKFF

19. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 19 JKFF

20. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 20 Characteristic Tables and Equations J KQ(t+1) 0 0 1 1 0 1 Q(t) 0 1 Q’(t) No change Reset Set Complement DQ(t+1) 0101 0101 Reset Set TQ(t+1) 0101 Q(t) Q’(t) No change Complement Q(t + 1) = D (D Flip-Flop) Q(t + 1) = JQ’ + K’Q (JK Flip-Flop) Q(t + 1) = TQ’ + T’Q (T Flip-Flop)

21. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 21 D A = A  x  y

22. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 22 Mealy Machine Outputs dependent on inputs and state variables. Are inputs synchronized with clock?

23. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 23 Moore Machine Comb. Circuit State Registers Output Input Outputs dependent on state variables only. Comb. Circuit

24. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 24 4-Bit Register  A register is a group of flip-flops, read/written as a unit.  A register that goes through a prescribed sequence of states upon the application of input pulses is called a counter.

25. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 25 Register with Parallel Load 1 1 1 1 1 1 0 0 0 0 0 0 0 0 I0I0 I1I1 I2I2 I3I3 I0I0 I1I1 I2I2 I3I3 I0I0 I1I1 I2I2 I3I3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 I0I0 I1I1 I2I2 I3I3 I0I0 I1I1 I2I2 I3I3

26. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 26 Shift Register Edge trigger or level trigger? 1 0 1 1 10 100

27. Department of Electronic Engineering, FJU Verilog HDL: A Guide to Digital Design and Synthesis 27 Synchronous Counter  No need to go through a sequential logic design process.  The flip-flop in the least significant position is complemented with every pulse. A flip-flop in any other position is complemented when all the bits in the lower significant positions are equal to 1.