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Digital Design Lecture 10 Sequential Design. State Reduction Equivalent Circuits –Identical input sequence –Identical output sequence Equivalent States.

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Presentation on theme: "Digital Design Lecture 10 Sequential Design. State Reduction Equivalent Circuits –Identical input sequence –Identical output sequence Equivalent States."— Presentation transcript:

1 Digital Design Lecture 10 Sequential Design

2 State Reduction Equivalent Circuits –Identical input sequence –Identical output sequence Equivalent States –Same input  same output –Same input  same or equivalent next state

3 g & e equivalent, f & d equivalent State a b c d e f g Next State x=0 x=1 a b c d a d e f a f g f a f Output x=0 x=1 0 0 1

4 State Assignment State a b c d e Binary 000 001 010 011 100 Gray Code 000 001 011 010 110 One-Hot 00001 00010 00100 01000 10000

5 Reduced State Table: Binary State Assignment State 001 010 011 100 101 Next State x=0 x=1 000 001 010 011 000 011 100 011 000 011 Output x=0 x=1 0 0 1 Table 5-10

6 Design Procedure Develop State Diagram From Specs Reduce States Assign Binary values to States Write Binary-coded State Table Choose Flip-Flops Derive Input and Output Equations Draw the Logic Diagram

7 Develop State Diagram: Sequence Detector Detect 3 or more 1s in sequence (a Moore Model)

8 D Flip-Flop Input Equations A(t+1) = D A (A,B,x) =  (3,5,7) B(t+1) = D B (A,B,x) =  (1,5,7) y(A,B,x) =  (6,7) State A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Next State A B 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 Output y 0 0 0 0 0 0 1 1 Input x 0 1 0 1 0 1 0 1 Input equations come directly from the next state in D Flip-Flop design

9 Simplified Boolean Equations

10 Sequence Detector: D Flip-Flops

11 Using JK or T Flip-Flops 1.Develop Excitation Table Using Excitation Tables Table 5-12 KXX10KXX10 J01XXJ01XX Q(t+1) 0 1 0 1 JK Flip-Flop Q(t) 0 0 1 1 T0110T0110 T Flip-Flop Q(t+1) 0 1 0 1 Q(t) 0 0 1 1

12 State Table: JK Flip-Flop Inputs B00110011B00110011 A00001111A00001111 Present State x00001111x00001111 Input B01010110B01010110 A00101110A00101110 Next State KA01010110KA01010110 JA00101110JA00101110 KB01010110KB01010110 JB00101110JB00101110 Flip-Flop Inputs Table 5-13

13 Maps for J and K Input Equations

14 JK Flip-Flop Sequence Detector

15 Synthesis Using T Flip-Flops: Designing a Counter

16 3-Bit Counter State Table A100110011A100110011 A200001111A200001111 Present State A001010101A001010101 A101100110A101100110 A200011110A200011110 T A1 0 1 0 1 0 1 1 1 T A2 0 0 0 1 T A0 1 1 1 1 Flip-Flop InputsNext State A010101010A010101010

17 3-Bit Counter Karnaugh Maps

18 The 3-Bit Counter


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