1. PreProcessor Upgrade Issues Victor Andrei Kirchhoff-Institut für Physik (KIP) Ruprecht-Karls-Universität Heidelberg L1Calo Weekly Meeting, 10 January 2013

2. SUM ch1 ch2 ch3 ch4 BCMUX FPGA (Spartan-6) MCM #1 10 LVDS-Tx MCM #16 CP1 CP2 JEP JEPJEP CPCP Virtex-II 32x 16x 480Mb/s FPGA J2J2 power PPM LCD (f/o & routing) to CP (LVDS cables) to JEP (LVDS cables) to DAQ r/o data RGTM V.Andrei, KIP L1Calo Weekly Meeting, 10/01/2013 2 Current System

3. ch1 ch2 ch3 ch4 BCMUX FPGA (Spartan-6) MCM #1 MCM #16 CP1 10 CP2 JEP MUX + LVDS-Tx LVDS-Tx JEPJEP CPCP Spartan-6/Artix-7 32x 16x 480Mb/s 960Mb/s FPGA J2J2 power PPM nLCD (f/o & routing) to CP (LVDS cables) to JEP (LVDS cables) to DAQ r/o data RGTM V.Andrei, KIP L1Calo Weekly Meeting, 10/01/2013 3 Phase-I: first solution

4. ch1 ch2 ch3 ch4 BCMUX FPGA (Spartan-6) MCM #1 MCM #16 CP1 10 CP2 JEP MUX + LVDS-Tx LVDS-Tx CPCP JEPJEP JEPJEP CPCP nLCD (f/o & routing) Spartan-6/Artix-7 32x 16x 480Mb/s 960Mb/s FPGA SNAP12 to CP (LVDS cables) to JEP (LVDS cables) J2J2 to DAQ r/o data Xilinx 7 Series Rear Extension power PPM to jFEX (optic fibers) RGTM V.Andrei, KIP L1Calo Weekly Meeting, 10/01/2013 4 Phase-I: second solution (A) ? FPGA

5. SUM ch1 ch2 ch3 ch4 BCMUX FPGA (Spartan-6) MCM #1 10 LVDS-Tx MCM #16 CP1 CP2 JEP JEPJEP CPCP Virtex-II 32x 16x 480Mb/s FPGA J2J2 power PPM LCD (f/o & routing) to DAQ r/o data RGTM V.Andrei, KIP L1Calo Weekly Meeting, 10/01/2013 5 to CP (LVDS cables) to JEP (LVDS cables) Xilinx 7 Series Rear Extension to jFEX (optic fibers) FPGA SNAP12 CPCP JEPJEP Phase-I: second solution (B)