1. Micropipeline design in asynchronous circuit Wilson Kwan M.A.Sc. Candidate Ottawa-Carleton Institute for Electrical & Computer Engineering (OCIECE) Carleton University Ottawa, Canada March 18, 2002

2. Outline What is micropipeline in asynchronous circuit? Basic building blocks of the micropipeline. Difference between two phase signalling and four phase signalling protocol. Improvement on the micropipeline. - Double edge triggered D-flop flip Future work of micropipeline.

3. What is micropipeline? Micropipeline is a basic building block in an asynchronous circuit. Global clock signal is replaced by the local handshaking communication protocol. Request and acknowledge signals are primarily used to communicate between two stage of pipeline.

4. Basic building blocks of the micropipeline Basic building blocks of the micropipeline Muller C-elements Merger XOR Toggle Latch (capture-pass latch in conventional two phase micropipeline) C Toggle

5. Basic building blocks of the micropipeline (cont’) C Toggle Rin Latch Aout Data out Data in Ain Rout A two-phase latch control circuit with two to four phase converter Rin Ain Aout Rout

6. Basic building blocks of the micropipeline (cont’) A four-phase latch control circuit C Rin Latch Aout Data out Data in Ain Rout Lt

7. Basic building blocks of the micropipeline (cont’) Muller C-element: (static C-element) X Y Vss Vdd Z

8. Difference between two phase signalling and four phase signalling protocol Two-phase handshake protocol: Four-phase handshake protocol: Data Request Acknowledge Data Request Acknowledge

9. Improvements on the micropipeline design To increase the performance and energy efficieny of the micropipeline: -Two phase double edge-triggered D flip-flops replace the “Capture-pass” latches

10. Improvements on the micropipeline design- ( Double edge triggered D-flop flip) 2 phase pipeline circuit with double edge- triggered D-FF’s C RinAout Ain Din Dout DQ Rout tdtd T event-Q t A-A’

11. Improvements on the micropipeline design- ( Double edge triggered D-flop flip) For this pipeline circuit to function correctly, two time constraints must be met : Data setup time (t su ): t d > T i event-Q +T i logic + t i+1 su – t i+1 R-A’ Data hold time (t h ): t i A-A’ + t i min cycle time +T i logic > t i+1 h where forward latency = T event-Q +T logic + t su backward latency = t R-A’

12. Improvements on the micropipeline design- ( Double edge triggered D-flop flip) Double edge-triggered D-flip-flop:

13. Improvements on the micropipeline design- ( Double edge triggered D-flop flip) Delay, area and energy/cycle comparison: Double edged trigger latch Capture and pass latch Who wins Latency, ns2.63.6DET Cycle time, ns3.99.8DET Area3321Capture and pass Energy/cycle2.43DET

14. Future work of micropipeline GasP pipeline : each stage operates at the speed of a three-inverter ring oscillator.

15. References  I.E. Sutherland, “Micropipeline,” Comm. ACM, vol. 32, no.6, pp. 720-738, June 1989.  K.Y. Yun, P.A. Beerel, and J. Arceo, “High Performance Asynchronous Pipeline Circuits,” Proc. Int’l Symp. Advanced Research in Asynchronous Circuit and Systems pp. 17-28, 1996  Stephen B, Furber and Paul Day, “Four-Phase Micropipeline Latch Control Circuits,” Vol. 4, no.2, June 1996.