1. Computer Architecture Lecture 3: Logical circuits, computer arithmetics Piotr Bilski

2. Arithmetic-Logical Unit (ALU) Performs arithmetic-logical operations Calculations are performed on the binary system numbers (Boole’s algebra) ALU CU registers state pointers (flags) registers

3. Number representations Integer numbers: Real numbers: 61 10 = 0 0 1 1 1 1 0 1 2 2727 2626 2525 2424 23232 2121 2020 1,6328125 10 = 1, 1 0 1 0 0 0 1 0 2 LSB MSB

4. Integer numbers (fixed point representation) Representation of the unsigned number A: Sign-magnitude representation: Two’s complement (U2):

5. Examples (sign-magnitude) 21 10 = 00010101 2 -21 10 = 10010101 2 0 10 = 00000000 2 0 10 = 10000000 2 double zero representation addition and subtraction requires analysis of signs and magnitudes

6. Integer systems characteristics Adding the opposite number Additional algorithm Subtraction When signs of the operands are equal and result's opposite Sign and magnitude analysis Overflow Additional bits filled with a sign Additional bits = 0 MSB  sign Increase bits number Two’s complementChange MSBNegation OneTwoZero representations -2 n-1 to 2 n-1 -1-2 n-1 +1 to 2 n-1 -1Range Two’s complementSign-magnitudeCharacteristics

7. Arithmetic operations on integers (1) Negation: Sign-magnitude 00010101 (21) +10000000 10010101 (-21) Two’s complement 00010101 (21) 11101010 NEG(21) +00000001 11101011 (-21)

8. Arithmetic operations on integers (2) Conversion between lengths: Sign-magnitude 00010101 (21) 8b 00000000 00010101 (21) 16b 10010101 (-21) 10000000 00010101 (-21) 16b Two’s complements 00010101 (21) 8b 00000000 00010101 (21) 16b 11101011 (-21) 8b 11111111 11101011 (-21) 16b

9. Arithmetic operations on integers (3) Addition: Sign-magnitude 00011001 (25) +00001101 (13) 00100110 (38) 10011001 (-25) +10001101 (-13) 10100110 (-38) 10011001 (-25) x0011001 +00001101 (13) x1110010 NEG(13) 10001100 (-12) 0001011 +0000001 10001100 (-12) 10001101 (-13) x0001101 +00011001 (25) x1100110 NEG(25) 00001100 (12) 1110011 R 00001100 NEG(R)

10. Arithmetic operations on integers (4) Addition: Two’s complements 00011001 (25) +00001101 (13) 00100110 (38) 11100111 (-25) +11110011 (-13) 11011010 (-38) 11100111 (-25) +00001101 (13) 11110100 (-12) 11110011 (-13) +00011001 (25) 00001100

11. Arithmetic operations on integers (5) Multiplication Unsigned integers: 0111 (7) 4b 0101 (5) 4b 00000111 00000000 00011100 00000000 00100011 (35) 8b !!

12. Increasing effectiveness of the multiplication Every partial result can be summed at once (fewer registers!) Multiplying by zero is only bit shifting!

13. Hardware realization of the unsigned integers multiplication Carry (C) Accumulator (A)

14. Example of the hardware algorithm’s work C A Q M 0 0000 0101 0111 starting values 0 0111 0101 0111 add 0 0011 1010 0111 shift right 0 0001 1101 0111 move 0 1000 1101 0111 add 0 0100 0110 0111 shift 0 0010 0011 0111 move 0 0010 0011 0111 result

15. Multiplication in Two’s complement representation Signed integers: 1001 (-7)  multiplier 0011 (3)  multiplicand 11111001 11110010 11101011 (-21) Different interpretation of the binary shifting Negative number must be represented in the two’s complement code

16. Realization of the multiplication in the Two’s complement code –Booth’s algorithm A  0, Q -1  0, LOAD(M, Q) Bit counter = n Right shifting A, Q, Q -1 Bit counter = bit counter - 1 A  A - M A  A + M START Q 0, Q -1 STOP Bit count.=0 YES =01 =10 =11 =00 NO

17. Example of the Two’s complement code multiplication (7 x 3 operation) A Q Q -1 M 0000 0011 0 0111 starting values 1001 0011 0 0111 subtract 1100 1001 1 0111 shift arithmetically 1110 0100 1 0111 shift arithmetically 0101 0100 1 0111 add 0010 1010 0 0111 shift arithmetically 0001 0101 0 0111 shift arithmetically 0001 0101 0 0111 result

18. Division of unsigned integers A  0, LOAD(M, Q) Bit counter = n Bit counter = bit counter - 1 Q 0  1 Q 0  0 A  A + M START A < 0? STOP Bit count.=0 YES NO Move A,Q left A  A - M

19. Division of integers in Two’s complement representation LOAD(A, M, Q) Bit counter = n Bit counter = bit counter - 1 Q 0  0 Q 0  1 START Oper. successful? STOP Bit count.=0 YES NO Move A,Q left A  A - M signs A, M identical? A  A + M NO YES restore A

20. Example of the Two’s complement representation division (–7/3 operation) A Q M 1111 1001 0011 starting values 1111 0010 0011 shift left 0010 add 1111 0010 0011 restore 1110 0100 0011 shift left 0001 add 1110 0100 0011 restore 1100 1000 0011 shift left 1111 add 1111 1001 0011 set Q 0 = 1 1111 0010 0011 shift left 0010 add 1111 0010 0011 restore 1111 0010 0011 result

21. Floating point representation Used to represent very small and very large numbers Form the following number: where: m – mantissa c – exponent b - base

22. Examples 1.24 x 10 7 (1.24e7) 5.82 x 10 -21 0.010110 x 2 110101 0.001001 x 16 101 Format of the 32-bit floating point number: 8 bits 23 bits sign exponent mantissa

23. Representation of the floating point binary number 1,6328125 x 2 20 = 1.1010001 x 2 10100 1 0,6328125 x 21,265625 0,265625 0 0,265625 x 20,53125 1 0,53125 x 21,0625 0,0625 0 0,0625 x 20,125 0 0,125 x 20,25 0 0,25 x 20,5 1 0,5 x 21,0 0

24. Representation of the binary floating-point number 1,6328125 x 2 20 = 1.1010001 x 2 10100 10010011 10100010000000000000000 0 Exponent is a displaced number at 127, so 20 = 127 + 20 = 147 (as above)

25. Normalization of the floating- point number Exponent is changed, so the first mantissa’s digit before the comma was non-zero Because the non-zero number is 1, it does not have to be stored

26. Range and accuracy of the floating-point numbers For the 32-bit number: Exponent is 8-bit, so range is +-2 256 Mantissa is 23-bit, so accuracy is 2 -23 = 1.2 x 10 -7 We make a compromise between the accuracy and range

27. Density of the floating point numbers -n 0 n 2n 4n negative overflow positive overflow zero negative underflow positive underflow

28. Standard IEEE 754 Apllied standard of storing floating point numbers Refers to the 32- i 64-bit numbers Exponent of length, respectively, 8 i 11 bits Default base is 2 Predefined formats for the indirect calculations

29. Special values in IEEE 754 c = 0, m = 0 – positive or negative zero c = 11111111, m = 0 – positive or negative infinity c = 0, m  0 - denormalized number (bit on the left from the comma is zero!) c = 11111111, m  0 - NaN

30. Floating point arithmetics Basic operations:

31. Addition and subtraction 1.Checking for zeros 2.Equalization of mantissas 3.Adding or subtracting of mantissas 4.Result normalization Example: (123 x 10 0 )+(456 x 10 -2 )=(123 x 10 0 )+(4,56 x 10 0 ) = = 127,56 x 10 0

32. Multiplying and dividing 1.Checking zeros 2.Adding exponents and subtracting shifted values from the sum 3.Checking for exponent overflow and underflow 4.Multiplication of the mantissas considering signs (sign-magnitude representation!) 5.Rounding and normalization of the multiplication result

33. Logical structures (1) Basic gates: ABAB Y Y = A AND B ABAB Y A Y Y = A OR B A = NOT Y ABY000010100111ABY000010100111 ABY000011101111ABY000011101111 AY1001AY1001

34. Logical structures (2) Additional gates: ABAB Y Y = A NAND B ABAB Y Y = A NOR B ABY001011101110ABY001011101110 ABY001010100110ABY001010100110 ABAB Y = A XOR B Y ABY000011101110ABY000011101110

35. Logical structures (3) Half-adder ABAB SCSC ABSC0000011010--11--ABSC0000011010--11-- A S B C

36. Logical structures (4) Adder A S B C A S B C CiABCiAB SCoSCo A B C i S C o 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 1 0 0 11 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1

37. Logical structures (5) 4-bit adder A 0 B 0 A 1 B 1 A 2 B 2 A 3 B 3 0 S 0 S 1 S 2 S 3 C1C1 C2C2 C3C3 C4C4