1. COE4OI5 Engineering Design Chapter 2: UP2/UP3 board

2. Copyright S. Shirani 2 UP3 UP3 board contains a Cyclone FPGA, several memory devices and a wide range of I/O features Two versions of the board are available one based on C6 and the other one based on C12 FPGA. The FPGA and memory devices can be programmed using a JTAG ByteBlaster II cable attached to the PC printer (parallel) port The printer port mode of the PC should be set in the PC’s BIOS to ECP or EPP.

3. Copyright S. Shirani 3 UP3 An on-board clock oscillator and clock chip provides several clock signals that are selectable with the board’s jumpers

4. Copyright S. Shirani 4 Figure 2.1 The Altera UP 3 board.

5. Copyright S. Shirani 5 Figure 2.2 The Altera UP 3 board’s features.

6. Copyright S. Shirani 6 Table 2.1 UP 3 Board’s Cyclone FPGA Features Cyclone FPGA FeatureEP1C6Q240EP1C12Q240 Logic Elements (LEs)5,98012,060 4K bit RAM blocks (M4Ks) 2052 Total Internal RAM bits92,160239,616 Phase Locked Loops (PLLs) 22 User I/O pins185173

7. Copyright S. Shirani 7 Memory In addition to the Cyclone FPGA’s internal memory, the UP3 has several external ROM and RAM memory Capacities of external memories are much larger than internal memory but they have a longer access time FPGA processor cores (e.g., Nios) use external memory for program and data memory and the FPGA’s internal memory for registers and cache The serial flash chip is used to automatically load the FPGA’s serial configuration data at the power up in systems where you do not want to download the configuration data through the Byteblaster.

8. Copyright S. Shirani 8 Table 2.2 UP 3 Board’s Memory Features Memory DeviceSizePart Number SRAM64K by 16 bitsISSI IS61C6416 SDRAM1M by 16 bitsISSI IS42S16400B Flash Memory1M by 16 bitsToshiba TC58FVB106AFT-70 I 2 C EEPROM16K by 1bitISSI IS24C16 Serial Flash Memory1M by 1bitAltera EPCS1

9. Copyright S. Shirani 9 I/O For most I/O devices, the UP3 board’s hardware provides only an electrical interface to the FPGA’s I/O pins Logic that provides a device interface circuit or controller will need to be constructed using the FPGA’s internal logic (UP core functions) Also remember to assign pins as shown in the tutorial to avoid turning on several of the memory devices at the same time Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins

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11. Copyright S. Shirani 11 Table 2.3 Overview of the UP 3 Board’s I/O Features I/O Device DescriptionHardware Interface Needed USB 1.1Full Speed and Low SpeedProcessor & USB SIE engine core Serial PortRS 232 Full ModemUART to send and receive data Parallel PortIEEE 1284State machine or Proc. for handshake PS/2 PortPC Keyboard or MouseSerial Data - PS/2 state machine VGA Port for Video Display on Monitor RGB three 1-bit signals provide 8 colorsState machine for sync signals & user logic to generate RGB color signals IDE PortConnectorProcessor & IDE Device Driver Reset SwitchUse for Global ResetMust use a reset in design Pushbutton Switches4 Non-debounced (0=HIT)Most applications will need a switch debounce Circuit Expansion CardSanta Cruz Long 72 I/ODepends on expansion card used LEDs4 User Definable (1=ON)None LCD Display16 Character by 2 line ASCII Characters State machine or Processor to send ASCII characters and LCD commands Real Time ClockI 2 C clock chipSerial Data - I 2 C state machine DIP Switch4 Switches (1=ON)None or Synchronizer Circuit

12. Copyright S. Shirani 12 Table 2.4 UP 3 Board’s most commonly used FPGA I/O pin names and assignments Pin NamePin#Pin I/O TypeFunction of Pin PS2_CLK12BidirectionalPS2 Connector PS2_DATA13BidirectionalPS2 Connector RESET23InputPower on or SW8 pushbutton reset ( Reset = 0 ) USB_CLK29InputUSB 48MHz Clock - jumper USER_CLOCK38InputExternal Clock from J2 Pin 2 PBSWITCH_448InputPushbutton SW4 (non-debounced, 0 = button hit) PBSWITCH_549InputPushbutton SW5 (non-debounced, 0 = button hit) LCD_E50OutputLCD Enable line LED_D653OutputLED D3 (0 = LED ON, 1= LED OFF) LED_D554OutputLED D4 (0 = LED ON, 1= LED OFF) LED_D455OutputLED D5 (0 = LED ON, 1= LED OFF) LED_D356OutputLED D6 (0 = LED ON, 1= LED OFF) PBSWITCH_657InputPushbutton SW6 (non-debounced, 0 = hit) DIPSWITCH_158InputDIP Switch SW3 #1 ( ON = 1, OFF = 0) DIPSWITCH_259InputDIP Switch SW3 #2 ( ON = 1, OFF = 0) DIPSWITCH_360InputDIP Switch SW3 #3 ( ON = 1, OFF = 0)" DIPSWITCH_461InputDIP Switch SW3 #4 ( ON = 1, OFF = 0)

13. Copyright S. Shirani 13 Table 2.4 (continued) UP 3 Board’s most commonly used FPGA I/O pin names and assignments Pin NamePin#Pin I/O TypeFunction of Pin PBSWITCH_762InputPushbutton SW7 (non-debounced, 0 = hit) LCD_RW73OutputLCD R/W control line MEM_DQ[0]94BidirectionalMemory/LCD Data Bus MEM_DQ[1]96(133)BidirectionalMemory/LCD Data Bus MEM_DQ[2]98BidirectionalMemory/LCD Data Bus MEM_DQ[3]100BidirectionalMemory/LCD Data Bus MEM_DQ[4]102(128)BidirectionalMemory/LCD Data Bus MEM_DQ[5]104BidirectionalMemory/LCD Data Bus MEM_DQ[6]106BidirectionalMemory/LCD Data Bus LCD_RS108OutputLCD Register Select Line MEM_DQ[7]113BidirectionalMemory/LCD Data Bus VGA_GREEN122OutputVGA Connector Green Video Signal CPU_CLOCK153InputCPU Clock 100 or 66MHz - jumper VGA_BLUE170OutputVGA Connector Blue Video Signal VGA_VSYNC226OutputVGA Connector Vert Sync Signal VGA_HSYNC227OutputVGA Connector Horiz Sync Signal VGA_RED228OutputVGA Connector Red Video Signal

14. Copyright S. Shirani 14 UP2/MAX UP2 board supports both a MAX and a FLEX device. The devices can be programmed using a JTAG ByteBlaster II cable attached to the PC printer (parallel) port Jumpers on the board select which device is programmed. The MAX device is connected to two seven segment LED displays, two eight-position DIP switches, sixteen LEDs Two push buttons can be connected to the MAX using jumper wires Circuit board holes are provided for an additional 60-pin expansion header that can be added to connect external hardware

15. Copyright S. Shirani 15 Figures 2.1 and 2.2 The Altera UP 1 board.

16. Copyright S. Shirani 16 Table 2.1 UP 1 device selection jumpers for programming.

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18. Copyright S. Shirani 18 UP2/FLEX FLEX device is attached to a VGA connector, a PS/2 mouse and keyboard port, two seven segment displays, an eight- position DIP switch and two push buttons. To generate video output, mouse or keyboard input, an interface must be designed using logic inside the FLEX device (UP core functions) Circuit board holes are provided for three 60-pin expansion header that can be added to connect external hardware Do NOT connect high current devices such as motors or relay coils directly to FPGA I/O pins

19. Copyright S. Shirani 19 Table 2.4 UP 1 Board 10K20RC240 FLEX CHIP I/O pin assignments.

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