1. Sec Mirror Updates Firenze Feb 2, 2007

2. Sec Mirror Updates Firenze Feb 2, 2007

3. Sec Mirror Updates Firenze Feb 2, 2007 Sec Mirror Electronics Upgrades: Overview 1. Digital Control System: FPGA => DSP 2. Capacitance Sensor: Search for a different proximity sensor Estimate the real formula of the capacitance / stray capacitance Make a linear dependency between the measured voltage and the gap Search for a single capacitance-to-DN converter chip Test upgrades to the current circuit Test different approaches FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

4. Sec Mirror Updates Firenze Feb 2, 2007 Schematic of adaptive optics system Feedback loop: next cycle corrects the (small) errors of the last cycle FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

5. Sec Mirror Updates Firenze Feb 2, 2007 LBT672 control system global layout FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

6. Sec Mirror Updates Firenze Feb 2, 2007 DSP Role FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

7. Sec Mirror Updates Firenze Feb 2, 2007 FPGA vs DSP What can an FPGA do for real-time video processing compared to a DSP device? The parallel processing capability of an FPGA device meets performance requirements within a single device vs multiple DSP devices DSP device-based designs have traditionally included FPGAs on board for glue logic and processor peripherals. Now, primary DSP functionality can also be handled by the FPGA, including the glue logic, in one device. The integration of hundreds of processors in a real- time design is non-trivial and provides serious complications including design complexity, form factor, power consumption, development time and cost. FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

8. Sec Mirror Updates Firenze Feb 2, 2007 FPGA vs DSP (ELT) Number of actuators: 7000+ Power consumption of the actuators: 3kW+ The computational power is related to the square of the number of channels Maintaining this control concept, we could have an increase of up to two orders of magnitude of the number of DSPs! FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

9. Sec Mirror Updates Firenze Feb 2, 2007 FPGA vs DSP (summary) Design complexity  Power consumption  Development time  Cost  Size  System complexity  Performance ? ? Experience/History  DSP FPGA FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

10. Sec Mirror Updates Firenze Feb 2, 2007 What we can do… Test a prototype to verify the feasibility Split the design into modules Outsource the modules to collaborating groups …since: Human resources are poor (numerically) The development time is quite long (3+ yrs) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

11. Sec Mirror Updates Firenze Feb 2, 2007 Actel Evaluation Kit FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

12. Sec Mirror Updates Firenze Feb 2, 2007 Capacitive sensors: current approach FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

13. Sec Mirror Updates Firenze Feb 2, 2007 Adopted formula: C =  A / d (for the parallel-plate capacitor) One plate has a hole => the area is reduced by 1/3, but more important, the effect of the internal edge is not negligible One plate is not plane (distortion of the magnet) => the formula is dynamically changing and it depends also on the behavior of the surrounding actuators Estimate the capacitance (also the stray capacitances) to have an idea of the dynamical behavior and of the direct/inverse dependency Estimation of the REAL capacitance FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

14. Sec Mirror Updates Firenze Feb 2, 2007 Next generation? FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

15. Sec Mirror Updates Firenze Feb 2, 2007 Next generation? (2) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

16. Sec Mirror Updates Firenze Feb 2, 2007 Next generation? (3) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

17. Sec Mirror Updates Firenze Feb 2, 2007 The main improvements are reported hereafter: Embedded signal generator. The main advantage is that in this way the noise pickup due to ground level fluctuations observed in the present implementations (where the reference signal is common to all capacitive sensors) can be dramatically reduced Selection of critical components. The new design is entirely based on single supply, low voltage technology Direct conversion of the analog output and digital de- modulation. This avoids the use of additional sample and hold circuitry on the sensor output, with benefit on noise and bandwidth On-board analog to digital conversion. In this way, the noise pick-up along transmission cables is eliminated Board routing to reduce the effects of stray capacitances and noise sources Next generation? (summary) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

18. Sec Mirror Updates Firenze Feb 2, 2007 Upgrades to current approach FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

19. Sec Mirror Updates Firenze Feb 2, 2007 Capacitive sensors: a small modification Dielectric Performance Comparison Table COGFilm CapacitorX7R Shock NoiseExcellent Good 3rd H DistortionExcellent Good ESRExcellentGood Resistance to Heat ExcellentGoodExcellent BDVExcellentGoodExcellent Temp Characteristics Excellent Good DC-Bias Characteristics Excellent Good FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

20. Sec Mirror Updates Firenze Feb 2, 2007 Upgrades to current approach (2) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach No switches Sine wave Conclusions

21. Sec Mirror Updates Firenze Feb 2, 2007 Output  Vout = 3,5 mV/pF The DC voltage is 2X the Vin RMS value FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

22. Sec Mirror Updates Firenze Feb 2, 2007 Upgrades to current approach (3) FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

23. Sec Mirror Updates Firenze Feb 2, 2007  Vout = 17,5 mV/pF No Common Mode DC voltage Output FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

24. Sec Mirror Updates Firenze Feb 2, 2007 Capacitive sensors: a different approach FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

25. Sec Mirror Updates Firenze Feb 2, 2007 Capacitive sensors: a different approach Sensitivity = 125mV/pF FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Conclusions

26. Sec Mirror Updates Firenze Feb 2, 2007 Conclusions FPGA vs DSP Cap sensor: Now DSP Role Next Generation? OUTLINES Upgrades to current Another Approach Potentially there is room for improvements in both the analog and digital aspects of the control system of the adaptive secondary mirror This could be an occasion to bring the development of this system back to our labs… …and also the money for these contracts could be used to consolidate and expand our staff Conclusions

27. Sec Mirror Updates Firenze Feb 2, 2007 End of capacitive sensors

28. Sec Mirror Updates Firenze Feb 2, 2007 Facilities Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES All are connected to the LAN 2 new (!) entries

29. Sec Mirror Updates Firenze Feb 2, 2007 Facilities: Tektronix DPO7104 Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES 1GHz Bandwidth 5 GS/s on all channels, 20 GS on one ch. 20 Megasamples Record Length on all channels, 80 MS on one ch. >250,000 wfms/s Maximum Waveform Capture Rate Pinpoint™ Triggering Provides the Most Flexible and Highest Performance Triggering, with over 1400 Combinations to Address Virtually Any Triggering Situation Save data directly to excel Zoom-in on four areas of interest simultaneously Basic spectral analysis 2 new (!) entries

30. Sec Mirror Updates Firenze Feb 2, 2007 Facilities: Tektronix TLA5201B Logic Analyzer Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES 34 Channel 2 GHz Timing with 125 ps MagniVu™ Acquisition 235 MHz State 512K Memory Depth Drag & Drop Triggering Flagging the Glitch Drag & Drop Measurements TS/TH Violation Triggering 2 new (!) entries

31. Sec Mirror Updates Firenze Feb 2, 2007 Facilities Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES Tektronix' Integrated View (iView™) data display enables digital designers to solve signal integrity challenges and effectively debug and verify their systems more quickly and easily. This integration allows designers to view time-correlated digital and analog data in the same display window, and isolate the analog characteristics of the digital signals that are causing systems failures. 2 new (!) entries

32. Sec Mirror Updates Firenze Feb 2, 2007 Facilities: a machine for drilling and routing of PCBs Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES Machine bed with universal fixture system, suitable for both clamps and ref. Pins KaVo high speed, 60,000 rpm spindle motor, 150 W, including 1/8" (3.175 mm) chuck Standard travel area: 320 x 270 x 30 mm Smallest drill diameter: 0.3mm Integral depth limiting device for (isolation) milling and engraving on uneven surfaces All machine parameters software controlled and configurable, including Z axis Step definition: 1 mil (= 0,0254 mm), precision +/- 1 step. 2 new (!) entries

33. Sec Mirror Updates Firenze Feb 2, 2007 Facilities: examples of boards for AGW Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES 2 new (!) entries

34. Sec Mirror Updates Firenze Feb 2, 2007 Facilities: new (old) entries Logic Analyzer Digital Oscilloscope PCB Prototyping Machine OUTLINES 2 new (!) entries Agilent 15 MHz Function/Waveform Generator TTi Digital Multimeter

35. Sec Mirror Updates Firenze Feb 2, 2007 End of Facilities