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16 – 17 Jul 02Andrew Werner TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT 1.

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Presentation on theme: "16 – 17 Jul 02Andrew Werner TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT 1."— Presentation transcript:

1 16 – 17 Jul 02Andrew Werner TRD Monitor Tube Readout Electronics: Shaping Peter Fisher, Bernard Wadsworth, Andrew Werner MIT 1

2 16 – 17 Jul 02Andrew Werner TRD Gas Monitor Tubes: Electronics 250 ns Proportional tubes & Fe55 source ~10 ns i t V t 3.2 V Multi-Channel Analyzer (MCA) Readout front end; Shaping stage ~ 10 uA MCA8000A 2

3 16 – 17 Jul 02Andrew Werner Front End Electronics: Overview Four channels: one digitally selectable at a given time Expects incoming current pulse of width 10 ns and height 10 uA; Total charge carried by pulse ~ 100 fC CSA Stage Gain: 10 V/pC Output scaled from 0 V - 3.2 V; Gaussian pulse with 250 ns width Runs off of 5V single supply; total DC current draw 60 mA typ, 85 mA max => Static power diss. 300 mW typ, 425 mW max 146 mV nom. DC offset at output 4:1 Analog Mux Charge Sensitive Amplifier Shaper (CR-RC) Charge Sensitive Amplifier Shaper (CR-RC) Charge Sensitive Amplifier Shaper (CR-RC) Charge Sensitive Amplifier Shaper (CR-RC) To MCA 3

4 16 – 17 Jul 02Andrew Werner Simplified Circuit Diagram (1) + - + - R1 D1 D2 C1 R2 C2 R3 R4 R5 C3 R6 R7 C4 + HV Vcc Vref - + U1 U2 Key component values: C1: 1 nF, 3 kV R2: 12 mOhm, C2: 2 pF, tau = 24 uS R3: 1.54 K R4: 80.6 Ohm R5: 910 K C3: 27 pF R6: 9.1 K R7: 27 K C4: 9.0 pF Vcc = +5V Reference is LT1460 (Linear), Vref = 2.5V ± 0.1% U1, U2: OPA357 (TI/BB) 4 Vref

5 16 – 17 Jul 02Andrew Werner Simplified Circuit Diagram (2) + - U11 ADG708 U12 R11 R12 R13 R14 C11 Vref A1 A0 CH3 CH2 CH1 CH0 To MCA R13 U11 is a 8:1 multiplexing switch; one of the inputs is connected to the output by the inputs S0 and S1. U12 eliminates the 2.5V offset and provides output to the MCA Component values: R11, R13: 1.0 K R12, R14: 2.0 K All values 1% R13: 100 Ohm 5 S3 S2 S1 S0 Vcc BIAS NETWORK C12

6 16 – 17 Jul 02Andrew Werner Board Layout Outsourced development of prototype board; surface mount Dimensions: 3.25” x 2.75” (82.5 mm x 69.9 mm) Four layers: Component, Solder, Ground, +5V Four slots for input capacitors; minimize possibility of dielectric breakdown Reference placed in cutaway section to minimize noise due to flexure of board 6

7 16 – 17 Jul 02Andrew Werner Schedule Board layout nearly complete, should be sent out for fabrication within this week or the next Testing, verification to begin soon Expected final delivery: September Thanks to Peter Fisher and Bernard Wadsworth of MIT LNS for help and guidance in the circuit design 7


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