1. ECE 353 Introduction to Microprocessor Systems
Week 2
Michael J. Schulte

2. Tutorial Reminder Wednesday, February 13th, 2008
Keil uVision3 tutorial 6:30-8:00pm EH1249

3. Topics Microprocessor Organization
Organization of Microprocessor Systems
Endian-ness
ARM History and Characteristics
ARM7TDMI Implementation
ADuC7026 Overview

4. Microprocessor Components
Register file
Program counter
General purpose registers
Hidden registers
ALU
Buses
Memory interface
Signal conventions
Control and timing unit

5. A Simple P Architecture
A less simple architecture

6. Instruction Set Architecture (ISA)
Complex Instruction Set (CISC)
Single instructions for complex tasks (string search, block move, FFT, etc.)
Usually have variable length instructions
Registers have specialized functions
Reduced Instruction Set (RISC)
Instructions for simple operations only
Usually fixed length instructions
Large orthogonal register sets

7. Register Architectures
Accumulator
One instruction operand comes from a dedicated register (the accumulator) closely coupled to the ALU.
Register-Memory
Instruction operands can be obtained from both registers and memory
Commonly used in CISC machines
Load-Store
All operands must be in general-purpose registers
Only a very limited number of instructions (loads/stores) can “touch” memory
Commonly used in RISC machines

8. Microprocessor System Organization
Memory Architectures
Von Neumann architecture
Harvard architecture
Input/Output (I/O)
Memory-mapped I/O
Isolated I/O
Examples
Programmer’s Model
aka Register View
Memory Maps

9. Endian-ness Byte Ordering for Little Endian vs. Big Endian Big Endian
Most Significant Byte (MSB)
Least Significant Byte (LSB)
Example: int x = 0x1234;
Big-endian Motorola, SPARC (big end in first byte)
Little-endian Intel (little end in first byte)
The MIPS processor and compilers support both the Big Endian and Little Endian byte-ordering conventions. The names Big Endian and Little Endian are used because of the apt analogy to the bloody feud in the classic children's book Gulliver's Travels (quod vide). The feud was between the two mythical islands, Lilliput and Blefescu, over the correct end (big or little) at which to crack an egg. In our case, the issue has to do with the "end" (most significant or least significant) of a multiple-byte data type.
With Big Endian ordering, the address of a multiple-byte data type is of its most significant byte (its "big end"), whereas with Little Endian ordering, the address is of its least significant byte (its "little end"). This is shown in Figure A.14. For structures declared in a high-level language, the order of bytes in memory will differ depending on the byte ordering and the particular data type, as shown for a C structure in Figure A.15.
Most UNIXes (for example, all System V) and the Internet are Big Endian. Motorola 680x0 microprocessors (and therefore Macintoshes), Hewlett-Packard PA-RISC, and Sun SuperSPARC processors are Big Endian. The Silicon Graphics MIPS and IBM/Motorola PowerPC processors are both Little and Big Endian (bi-endian).
The ARM7 can be implemented as bi-endian, but traditionally has been implemented as little-endian.
Memory Address +0 +1 +2 +3
Big Endian
Byte 0
Byte 1
Byte 2
Byte 3
MSB in the lowest (first) memory address
Little Endian
LSB in the lowest (first) memory address

10. ARM Ltd Founded in November 1990 Spun out of Acorn Computers
Designs the ARM range of RISC processor cores
Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the ARM architecture
Software tools, boards, debug hardware, application software, bus architectures, peripherals etc
The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor.
Other companies became interested in this processor, including Apple who were looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorn’s processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd.
Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies.
One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor design.

11. ARM Partnership Model
ARM’s business model centres around the principle of partnership. At the centre of this are ARM’s semiconductor partners who design, manufacture and market ARM-compliant products.
Having so many partner companies producing silicon executing the same instruction set is a very important part of ARM’s strength in the market place.
However each of our semiconductor partners bring their own unique strengths to the partnership - each having their own technologies, applications knowledge, product focus, culture, geography, and key customers.
In addition to our partnering with semiconductor companies, we also partner with a large number of other third parties to ensure that operating systems, EDA and software development tools, application software and design services are available for doing ARM based designs.
“ATAP” stands for ARM Technology Access Program. Creates a network of independent design service companies and equips them to deliver ARM-powered designs. Members get access to ARM technology, expertise and support. Members sometimes referred to as “Approved Design Centers”.

12. ARM Powered Products

13. ARM7 Characteristics Designed to be a simple, efficient RISC core
Small die area
Low power
Low interrupt latency
These characteristics enabled ARM to become dominant in the cell phone market.
Most cell phones contain a heterogenous multiprocessor SoC with an ARM and a DSP.
Advanced ARM designs (ARM9,10,11) have become much more sophisticated (i.e. Intel Xscale in PDAs), but have had less success in penetrating other markets where power consumption issues are not as severe.

14. ARM7TDMI Implementation
The ARM7TDMI uses the ARM v4T ISA.
All instructions are conditional
The ARM7TDMI is a basic load-store RISC
Sixteen GP registers (R15-R0) with banking
Three stage pipeline (FDE)
No caches
Support for ARM (32-bit) and Thumb (16-bit) instruction sets
Multiply-accumulate (MAC) unit
On-chip hardware debug support

15. ARM7TDMI Processor Block Diagram

16. ARM7TDMI Processor Core

17. Analog Devices ADuC7026 ARM7TDMI core Numerous digital peripherals
62kB flash, 8kB SRAM
In-circuit programmable, JTAG debug
41.78MHz PLL with programmable divider
Little-endian
Numerous digital peripherals
GPIO
Timers (GP x4 and watchdog/wake-up)
UART/I2C/SPI serial interfaces
3-phase PWM
External memory interface (16-bit multiplexed)
Analog input/output
12 in, 4 out
Voltage reference and temperature sensor

18. ADuC7026 Block Diagram

19. ADuC7026 Memory Map

20. ADuC7026 Pin-Out (LQFP-80)

21. Assessment
Team ConcepTest
In-Class Address Decoding Exercise

22. Wrapping Up
Week 3 reading is chapters 5, , 6.14 from the textbook, the ARM7TDMI Technical Reference Manual chapter 2, and Supplement #1 (LearnContent)
Pre-Quiz #2 to be done by Tuesday 2/5 at midnight
Homework #1 due Wednesday 2/6
Tutorial on Wednesday 2/13 from 6:30-8:00pm in EH1249

23. Team ConcepTest
A 32-bit word with value 0x54AF8 is stored in memory at address 0x00008DC44 in a little-endian system. Show the address and contents of each byte of memory used.
What type of operation is described by (PC)  (PC) – 0Ch?
A 20-bit address space has a 32KB RAM at base address 38000h, and a 128KB ROM at B0000h. Draw and label the memory map.

24. In-Class Exercise
Design decode logic for the following devices with the indicated control inputs:
64Kx8 ROM (/CS, /OE) at 0x04XXXX
1Mx8 RAM (/CS, /OE, /WE) at 0xA00000
Input Port (/OE) at 0xFXXX00
Output Port (/WR) at 0x1XXXXX
In all cases, assume a 24-bit address bus (A23:0) and control signals (/RD, /WR)

25. TMS320C671X Organization

26. Register View of a Simple P
aka “Von Neumann” or “Princeton” architecture

27. Register View of a Simple P with Isolated I/O space
Most microprocessors do NOT have isolated I/O. The Intel x86 microprocessors do.

28. Register View of a Simple P with Separate Code and Data Memories
aka “Harvard” architecture