1. Low-Power CMOS Logic Circuit Topic Review 1 Part I: Overview (Shaw) Part II: (Vincent) Low-Power Design Through Voltage Scaling Estimation and Optimization of Switching Activity Part III: (Shaw) Reduction of Switched Capacitance Adiabatic logic circuit

2. Low-Power CMOS Logic Circuit Topic Review 2 Introduction

3. Low-Power CMOS Logic Circuit Topic Review 3 Motivations:  Portability Notebook computer Portable communication devices Personal digital assistants (PDAs)  Green Computer "The computer must be designed to use only non-toxic materials, to be energy efficient, and to have minimal impact on the environment in every stage of its life cycle."  Reliability

4. Low-Power CMOS Logic Circuit Topic Review 4 Methods?  Device level: Device characteristics (e.g., threshold voltage), device geometries, and interconnect properties.  Circuit level: proper choice of circuit design styles, reduction of the voltage swing, and clocking strategies.  Architecture level: smart power management of various system blocks, utilization of pipelining and parallelism, and design of bus structure.  Algorithm level: minimize the number of switching events.

5. Low-Power CMOS Logic Circuit Topic Review 5 Overview Types of Power Consumption

6. Low-Power CMOS Logic Circuit Topic Review 6 Three main components (CMOS circuit): 1.Dynamic (switching) power consumption 2.Short-circuit power consumption 3.Leakage power consumption

7. Low-Power CMOS Logic Circuit Topic Review 7 1.Switching Power Dissipation: Charge-up: one-half of the energy drawn from the power supply is dissipated as heat in conducting pMOS transistors. Charge-down: no energy is drawn from the power supply during the charge-down phase, yet the energy stored in the output capacitance during the charge- up is dissipated as heat in the conducting nMOS transistors.

8. Low-Power CMOS Logic Circuit Topic Review 8 (Periodic input with ideally zero rise- and fall-times) Assumption: output undergoes transition Reality? Node transition rate can be slower than the clock rate! Node transition factor

9. Low-Power CMOS Logic Circuit Topic Review 9 Represents the parasitic capacitance associated with each node in the circuit (including the output node) Represent the corresponding node transition factor associated with that node

10. Low-Power CMOS Logic Circuit Topic Review 10 2.Short-Circuit Power Dissipation:

11. Low-Power CMOS Logic Circuit Topic Review 11 Conditions: smaller output load capacitance and larger input transition times

12. Low-Power CMOS Logic Circuit Topic Review 12 Conditions: Very small capacitive load Short-circuit power dissipationInput signal rise and fall times

13. Low-Power CMOS Logic Circuit Topic Review 13 Conditions: larger output load capacitance and smaller input transition times

14. Low-Power CMOS Logic Circuit Topic Review 14 3.Leakage Power Dissipation: Reverse diode leakage current & subthreshold current (Reverse diode leakage current)

15. Low-Power CMOS Logic Circuit Topic Review 15 Reverse bias voltage across the junction Reverse saturation current density. The typical reverse saturation current density is Junction area

16. Low-Power CMOS Logic Circuit Topic Review 16 (subthreshold current)

17. Low-Power CMOS Logic Circuit Topic Review 17 4.Examples of Actual Power Dissipation: ChipIntel 80386 DEC Alpha 21064Cell based ASIC Minimum feature size1.50.750.5 Number of gates36,808263,66610,000 Clock frequency16MHz200MHz110MHz Supply voltage5V5V3.3V3V3V Total power dissipation1.41W32W0.8W Logic gates32%14%9% Clock distribution9%32%30% Interconnect28%14%15% I/O drivers26%37%43%

18. Low-Power CMOS Logic Circuit Topic Review 18 In addition to the three major sources of power consumption in CMOS digital integrated circuits discussed in this section, some chips may also contain circuits which consume static power. One example is the pseudo-nMOS logic circuits which utilize a pMOS transistor as the pull-up device. Summary

19. Low-Power CMOS Logic Circuit Topic Review 19 Method #1: Reduction of Switched Capacitance System-Level Measures: 1.Large number of drivers and receivers sharing the same transmission medium 2.The parasitic capacitance of the long bus line.

20. Low-Power CMOS Logic Circuit Topic Review 20 Circuit-Level Measures: XOR logic CMOS circuit Pass-gate logic The capacitance is a function of the number of transistors that are required to implement a given function

21. Low-Power CMOS Logic Circuit Topic Review 21 Mask-Level Measures: The parasitic gate and diffusion capacitances of MOS transistors in the circuit typically constitute a significant amount of the total capacitance in a combinational logic circuit. Hence, a simple mask-level measure to reduce power dissipation is keeping the transistors (especially the drain and source regions) at minimum dimensions whenever possible and feasible.

22. Low-Power CMOS Logic Circuit Topic Review 22 Trade-off: Dynamic performance of the circuitPower dissipation minimum dimensions??

23. Low-Power CMOS Logic Circuit Topic Review 23 Method #2: Adiabatic Switching  Adiabatic switching is also called energy-recovery “ Adiabatic ” describe thermodynamic process that exchanges no heat with the environment  Keep potential drop switching device small  Allow the recycling of energy to reduce the total energy drawn from the power supply

24. Low-Power CMOS Logic Circuit Topic Review 24 Transition of the output: How much is the stored energy? Transition of the output: No charge is drawn from the power supply and the the energy stored in the load capacitance is dissipated in the nMOS network CMOS Switching

25. Low-Power CMOS Logic Circuit Topic Review 25 Adiabatic Switching:

26. Low-Power CMOS Logic Circuit Topic Review 26  Less dissipation only if: –Current is constant and  Least power dissipation <- slowest transition  Energy dissipation is not only depend on the capacitance and swing voltage, but also proportional to the output resistance.

27. Low-Power CMOS Logic Circuit Topic Review 27 Adiabatic amplifier circuit which transfers the complementary input signals to its complementary outputs through CMOS transmission gates An example of Adiabatic Switching:

28. Low-Power CMOS Logic Circuit Topic Review 28 The general circuit topology of a conventional CMOS logic gate The topology of an adiabatic logic gate implementing the same function Adiabatic Logic Gates:

29. Low-Power CMOS Logic Circuit Topic Review 29 Circuit diagram of an adiabatic CMOS

30. Low-Power CMOS Logic Circuit Topic Review 30 Stepwise Charging Circuits: A CMOS inverter circuit with a stepwise-increasing supply voltage

31. Low-Power CMOS Logic Circuit Topic Review 31 Equivalent circuit, and the input and output voltage waveforms of the CMOS inverter circuit

32. Low-Power CMOS Logic Circuit Topic Review 32 Analysis: Solving this differential equation with the initial condition

33. Low-Power CMOS Logic Circuit Topic Review 33 Stepwise driver circuit for capacitive loads. The load capacitance is successively connected to constant voltage sources Vi through an array of switch devices

34. Low-Power CMOS Logic Circuit Topic Review 34 Tradeoff!! Reduction of energy dissipation Expense of switching time

35. Low-Power CMOS Logic Circuit Topic Review 35 Adiabatic families:  Partially Adiabatic Logic –2N2P / 2N-2N2P –CAL (Clocked CMOS Adiabatic Logic) –TSEL (True Single Phase Adiabatic) –SCAL (Source-coupled Adiabatic Logic)  Fully Adiabatic Logic –PAL (Pass-transistor Adiabatic Logic) –Split-level Charge Recovery Logic (SCRL)

36. Low-Power CMOS Logic Circuit Topic Review 36 oo PC out in / in / out 2N2P Inverter vs CMOS Inverter o out in Vdd 2N2P Inverter CMOS Inverter Periodic ramp-like clocked power supply Q=CV I=Q/T;T

37. Low-Power CMOS Logic Circuit Topic Review 37

38. Low-Power CMOS Logic Circuit Topic Review 38

39. Low-Power CMOS Logic Circuit Topic Review 39

40. Low-Power CMOS Logic Circuit Topic Review 40 2N-2N2P Inverter The primary advantage of 2N-2N2P over 2N2P is that the addition of the cross-coupled Nfets results in non-floating data valid over 100% of the HOLD phase.

41. Low-Power CMOS Logic Circuit Topic Review 41 Analysis: Reset Phase: The high output will ride down only to Vt,p, rather than GND. Wait Phase: Floating at 0 and Vt,p Evaluation Phase: If State has not changed If changed(nonadiabatic power consumption is )

42. Low-Power CMOS Logic Circuit Topic Review 42  Cascades require four-phase clocks  Non-adiabatic occurs at brief interval in the beginning of the evaluation phase  Non-adiabatic dissipation proportional to  Both inverting and non-inverting output available Characteristics of 2N2P / 2N-2N2P

43. Low-Power CMOS Logic Circuit Topic Review 43 oo PCK F1 CX F0 F1 CX CAL Inverter Cascades require single-phase clock and two auxiliary square-wave clocks

44. Low-Power CMOS Logic Circuit Topic Review 44

45. Low-Power CMOS Logic Circuit Topic Review 45 Simulated switching energy-vs-frequency curves

46. Low-Power CMOS Logic Circuit Topic Review 46