1. Chapter 3 Decoder and Encoder Digital Logic Design III
وزارة التعليم العالي والبحث العلمي
جامعة الكوفة - كلية التربية – قسم علوم الحاسوب
Digital Logic Design III
Chapter 3
Decoder and Encoder
Dr. Wissam Hasan Mahdi Alagele

2. Decoder definition
Decoding is the conversion of an n-bit input code to an m-bit output code with n ≤ m ≤ 2n, such that each valid code work produces a unique output code.
Decoding is performed by a logic circuit called a decoder.

3. Binary Decoder Black box with n input lines and 2n output lines
Only one output is a 1 for any given input
Binary
Decoder n
inputs
2n outputs

4. Decoders A decoder has N inputs 2N outputs
A decoder selects one of 2N outputs by decoding the binary value on the N inputs.
The decoder generates all of the minterms of the N input variables.
Exactly one output will be active for each combination of the inputs.
What does “active” mean?

5. Princess Sumaya University
Digital Logic Design
Decoders
Extract “Information” from the code
Binary Decoder
Example: 2-bit Binary Number
Only one lamp will turn on 1 2 3
Binary Decoder x1 x0 1
Dr. Bassam Kahhaleh

6. n-to-m-line decoders Circuit has n inputs and m outputs and m ≤ 2n
Start with n=1 and m=2
This a 1-to-2 Line decoder – exactly one of the output lines will be active.

7. Princess Sumaya University
Digital Logic Design
Decoders
A decoder when n=2 and m=4
A 2-to-4 line decoder
Note that only one output is ever active
Binary Decoder I1 I0 y3 y2 y1 y0
I1 I0
Y3 Y2 Y1 Y0
0 0
0 1
1 0
1 1
Dr. Bassam Kahhaleh

8. Truth Table, 3-to-8 Decoder
Notice they are minterms

9. Schematic

10. Multi-Level 3-to-8

11. Princess Sumaya University
Digital Logic Design
Decoders
3-to-8 Line Decoder
Binary Decoder I2 I1 I0 Y7 Y6 Y5
Y4 Y3 Y2 Y1 Y0
Dr. Bassam Kahhaleh

12. Enable Enable is a common input to logic functions
See it in memories and today’s logic blocks

13. 2-to-4 with Enable

14. Princess Sumaya University
Digital Logic Design
Decoders
“Enable” Control
Binary Decoder I1 I0 E Y3 Y2 Y1 Y0 E
I1 I0
Y3 Y2 Y1 Y0
x x 1
0 0
0 1
1 0
1 1
Dr. Bassam Kahhaleh

15. Enable Used for Expansion

16. Princess Sumaya University
Digital Logic Design
Decoders
Expansion
I2 I1 I0
I2 I1 I0
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Binary Decoder I0 I1 E Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4
Dr. Bassam Kahhaleh

17. Princess Sumaya University
Digital Logic Design
Decoders
Active-High / Active-Low
I1 I0
Y3 Y2 Y1 Y0
0 0
0 1
1 0
1 1
I1 I0
Y3 Y2 Y1 Y0
0 0
0 1
1 0
1 1
Binary Decoder I1 I0 Y3 Y2 Y1 Y0
Binary Decoder I1 I0 Y3 Y2 Y1 Y0
Dr. Bassam Kahhaleh

18. Implementation Using Decoders
Princess Sumaya University
Digital Logic Design
Implementation Using Decoders
Each output is a minterm
All minterms are produced
Sum the required minterms
Example: Full Adder
S(x, y, z) = ∑(1, 2, 4, 7)
C(x, y, z) = ∑(3, 5, 6, 7) I2 I1 I0 Y7 Y6 Y5
Y4 Y3 Y2 Y1 Y0
Binary Decoder x y z
S C
Dr. Bassam Kahhaleh

19. Implementation Using Decoders
Princess Sumaya University
Digital Logic Design
Implementation Using Decoders I2 I1 I0 Y7 Y6 Y5
Y4 Y3 Y2 Y1 Y0
Binary Decoder x y z
S C I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Binary Decoder x y z
S C
Dr. Bassam Kahhaleh

20. Encoders An encoder has
2N inputs
N outputs
An encoder outputs the binary value of the selected (or active) input.
An encoder performs the inverse operation of a decoder.
Issues
What if more than one input is active?
What if no inputs are active?

21. Princess Sumaya University
Digital Logic Design
Encoders
Put “Information” into code
Binary Encoder
Example: 4-to-2 Binary Encoder
Only one switch should be activated at a time 1 2 3
Binary Encoder y1 y0 x1 x2 x3
x3 x2 x1
y1 y0
0 0
0 1
1 0
1 1
Dr. Bassam Kahhaleh

22. Princess Sumaya University
Digital Logic Design
Encoders
Octal-to-Binary Encoder (8-to-3)
Binary Encoder Y2 Y1 Y0 I7 I6 I5
I4 I3 I2 I1 I0
I7 I6 I5 I4 I3 I2 I1 I0
Y2 Y1 Y0
Dr. Bassam Kahhaleh

23. Encoder / Decoder Pairs
Princess Sumaya University
Digital Logic Design
Encoder / Decoder Pairs
Binary Encoder
Binary Decoder Y7 Y6 Y5
Y4 Y3 Y2 Y1 Y0 7 7 I7 I6 I5
I4 I3 I2 I1 I0 6 6 5 5 Y2 Y1 Y0 I2 I1 I0 4 4 3 3 2 2 1 1
Dr. Bassam Kahhaleh

24. Princess Sumaya University
Digital Logic Design
Multiplexers
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MUX Y I0 I1 I2 I3
S1 S0
Dr. Bassam Kahhaleh

25. Princess Sumaya University
Digital Logic Design
Multiplexers
2-to-1 MUX
4-to-1 MUX
MUX Y I0 I1 S
MUX Y I0 I1 I2 I3
S1 S0
Dr. Bassam Kahhaleh

26. Princess Sumaya University
Digital Logic Design
Multiplexers
Quad 2-to-1 MUX x3 x2 x1 x0
MUX Y I0 I1 S y3 y2 y1 y0
MUX A3 A2 A1 A0
S E Y3 Y2 Y1 Y0 B3 B2 B1 B0 S
Dr. Bassam Kahhaleh

27. Princess Sumaya University
Digital Logic Design
Multiplexers
Quad 2-to-1 MUX
MUX A3 A2 A1 A0
S E Y3 Y2 Y1 Y0 B3 B2 B1 B0
Extra Buffers
Dr. Bassam Kahhaleh

28. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y) = ∑(0, 1, 3)
x y F
0 0 1
0 1
1 0
1 1
MUX Y I0 I1 I2 I3
S1 S0 1 F
x y
Dr. Bassam Kahhaleh

29. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y, z) = ∑(1, 2, 6, 7)
MUX Y I0 I1 I2
I3 I4 I5 I6 I7
S2 S1 S0 1
x y z F 1 F
x y z
Dr. Bassam Kahhaleh

30. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(x, y, z) = ∑(1, 2, 6, 7)
x y z F 1
MUX Y I0 I1 I2 I3
S1 S0 z
F = z F z
F = z 1
F = 0
x y
F = 1
Dr. Bassam Kahhaleh

31. Implementation Using Multiplexers
Princess Sumaya University
Digital Logic Design
Implementation Using Multiplexers
Example F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F 1
MUX Y I0 I1 I2
I3 I4 I5 I6 I7
S2 S1 S0 D
F = D D
F = D D
F = D F
F = 0 D
F = 0 1
F = D 1
F = 1
F = 1
A B C
Dr. Bassam Kahhaleh

32. Multiplexer Expansion
Princess Sumaya University
Digital Logic Design
Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX Y I0 I1 I2 I3 I4 I5 I6 I7
S2 S1 S0
MUX Y I0 I1 I2 I3
S1 S0
MUX Y I0 I1 S
MUX Y I0 I1 I2 I3
S1 S0 1
0 0
Dr. Bassam Kahhaleh

33. Princess Sumaya University
Digital Logic Design
DeMultiplexers
DeMUX I Y3 Y2 Y1 Y0
S1 S0
S1 S0 Y3 Y2 Y1 Y0
0 0 I
0 1
1 0
1 1
Dr. Bassam Kahhaleh

34. Multiplexer / DeMultiplexer Pairs
Princess Sumaya University
Digital Logic Design
Multiplexer / DeMultiplexer Pairs
MUX
DeMUX Y7 Y6 Y5
Y4 Y3 Y2 Y1 Y0 7 7 I7 I6 I5
I4 I3 I2 I1 I0 6 6 5 5 4 4 Y I 3 3 2 2 1 1
S2 S1 S0
S2 S1 S0
Synchronize
x2 x1 x0
y2 y1 y0
Dr. Bassam Kahhaleh

35. DeMultiplexers / Decoders
Princess Sumaya University
Digital Logic Design
DeMultiplexers / Decoders
DeMUX I Y3 Y2 Y1 Y0
S1 S0
Binary Decoder I1 I0 E Y3 Y2 Y1 Y0 E
I1 I0
Y3 Y2 Y1 Y0
x x 1
0 0
0 1
1 0
1 1
S1 S0 Y3 Y2 Y1 Y0
0 0 I
0 1
1 0
1 1
Dr. Bassam Kahhaleh

36. Princess Sumaya University
Digital Logic Design
Three-State Gates
Tri-State Buffer
Tri-State Inverter
C A Y
0 x
Hi-Z
1 0
1 1 1 A Y C A Y C
Dr. Bassam Kahhaleh

37. Princess Sumaya University
Digital Logic Design
Three-State Gates
C D Y
0 0
Hi-Z
0 1 B
1 0 A
1 1 ? A Y C B
Not Allowed D A C B
A if C = 1
B if C = 0 Y=
Dr. Bassam Kahhaleh

38. Princess Sumaya University
Digital Logic Design
Three-State Gates I3 I2 Y I1 I0
Binary Decoder Y3 Y2 Y1 Y0 S1 I1 I0 E S0 E
Dr. Bassam Kahhaleh