2. 17 Sep 2002Embedded Seminar2 Outline The Big Picture Who’s got the Power? What’s in the bag of tricks?

3. 17 Sep 2002Embedded Seminar3 The Big Picture Phenomenal increase in processor speed 3GHz Pentium 4 by the end of the year Shrinkage in size Mobility highly desired BUT battery technology not improving at the same rate

4. 17 Sep 2002Embedded Seminar4 Batteries Not Included Nickel-based batteries Nickel-Iron The first rechargeable, old technology Nickel-cadmium and Nickel-Metal-Hydride High energy density – good for motors Lithium-based batteries Promising because lithium releases electrons easily Problem with battery life, dangerous to handle Others Zinc-air batteries – can work a laptop for 10 hours

5. 17 Sep 2002Embedded Seminar5 Some Terminologies Power is the rate of energy consumption Power ≠ energy Energy depends on how long you run the thing! Optimizing for speed = optimizing for energy? Some researchers look at average power

6. 17 Sep 20026 Back to Basics   P - substrate N + sourceN + drain Gate Gate oxide insulator          N-Channel Metallic Oxide Semiconductor Field Effect Transistor

7. 17 Sep 20027 Back to Basics – ACTION!                                 P - substrate N + sourceN + drain Gate Gate oxide insulator         + -                                 + - N-Channel Metallic Oxide Semiconductor Field Effect Transistor

8. 17 Sep 2002Embedded Seminar8 P-channel MOSFET N-channel MOSFET CMOS V DD GND Input: 0 = 0V 1 = +5V Output CMOS Inverter

9. 17 Sep 2002Embedded Seminar9 P-channel MOSFET N-channel MOSFET CMOS V DD GND Input: 0 = 0V Output = 0 CMOS Inverter

10. 17 Sep 2002Embedded Seminar10 P-channel MOSFET N-channel MOSFET CMOS V DD GND Input: 1 = +5V Output = 1 CMOS Inverter

11. 17 Sep 2002Embedded Seminar11 Power in CMOS P = total power V DD = supply voltage f = clock frequency N = switching (gate transition per clock cycle) I leak = leakage power I static = static power Q SC = quantity of charge carried by short-circuit current per transistion

12. 17 Sep 2002Embedded Seminar12 Power in CMOS Switching power Short-circuit powerLeakage power Static power Dynamic power Static power

13. 17 Sep 2002Embedded Seminar13 Switching Power Accounts for most (90%) of power Two major factor is supply voltage and frequency Voltage scaling Frequency scaling

14. 17 Sep 2002Embedded Seminar14 Short Circuit Power During switching, there is a short period of time when both gates are ON  a path from V DD to ground  power dissipation

15. 17 Sep 2002Embedded Seminar15 Leakage Power Diode leakage Source (and drain) together with substrate forms a diode At times, this diode can be reverse-biased during which current can leak Sub-threshold leakage Even when gate is not completely on, enough of a channel can form for some movement of charges from source to drain

16. 17 Sep 2002Embedded Seminar16 Static Power Reduced voltage feeding Both gates can be “weakly on” Weak current flow from V DD to ground Other parasitic current flows Due to imperfect manufacturing or operating conditions

17. 17 Sep 2002Embedded Seminar17 A Digression – The Problems Of Scaling down Latch-up effect Short-channel effect Punch-through effect Hot electron effect Gate erosion

18. 17 Sep 2002Embedded Seminar18 Latch-up Effect

19. 17 Sep 2002Embedded Seminar19 Tricks in the bag Voltage Scaling Frequency Scaling Power Gating

20. 17 Sep 2002Embedded Seminar20 Voltage Scaling Lower V DD For the same circuit and technology, this leads to higher gate delay Total delay, , is made up of two components,  =  1 +  2  1 is a constant  2  V DD

21. 17 Sep 2002Embedded Seminar21 Frequency Scaling Widely used in many processors Intel SpeedStep on mobile processors Leads to lower performance Obvious!

22. 17 Sep 2002Embedded Seminar22 Power Gating Turn off power to parts of the circuit Can be problematic for circuits with memory

23. 17 Sep 2002Embedded Seminar23 What About Memory? SRAM Implemented using CMOS DRAM Entirely different technology Implemented using capacitors

24. 17 Sep 2002Embedded Seminar24 SRAM CMOS SRAM Cell

25. DRAM Single Transistor DRAM cell

26. 17 Sep 2002Embedded Seminar26 Model or Measure? Hardware measurement Measures the amount of current consumed Depends on how the circuit is designed Cannot get core CPU power breakdowns

27. 17 Sep 2002Embedded Seminar27 Software Estimation SPICE simulation Very slow PowerMill from Synopsys CAD Tools Part of a lot of CAD tool chains, eg. Synopsys Architectural based simulation Eg: SimplePower, WATTCH etc.

28. 17 Sep 2002Embedded Seminar28 Putting it Together – System Power Reference: Marc A. Viredaz and Deborah A. Wallach, “Power Evaluation of a Handheld Computer: A Case Study”. Compaq Western Research Lab Technical Report 2001/1. May 2001. http://research.compaq.com/wrl/techreports/abstracts/2001.1.html

29. 17 Sep 2002Embedded Seminar29 Dealing with it System / OS Algorithms Architecture Circuit/Logic Technology

30. 17 Sep 2002Embedded Seminar30 Technology Low threshold, low voltage Various technological issues as discussed

31. 17 Sep 2002Embedded Seminar31 Circuit/Logic Even within CMOS, there are different types of logic families that consumes different amount of energy Transistor size Layout Asynchronous circuits Clocking consumes a lot of power Pipeline retiming

32. 17 Sep 2002Embedded Seminar32 Architecture / Compiler Trade off area for power

33. 17 Sep 2002Embedded Seminar33 Architecture / Compiler Trade off area for power Shorter wires less power Parallelism and concurrency Directives to allow compiler to do Voltage scaling Frequency scaling Power gating One more degree of freedom: activity

34. 17 Sep 2002Embedded Seminar34 Algorithms Low power algorithms Parallelism and concurrency A under-research area

35. 17 Sep 2002Embedded Seminar35 System / OS System level power management Heuristics for transiting between various power modes Operating environment sensitive power management Battery or plugged-in? Power-domain specific management schemes

36. 17 Sep 2002Embedded Seminar36 Reducing Processor Power Energy conscious code generation Reduce switching Instruction scheduling Use of Gray code instead of binary Low power modes Instruction compression Parallelism and concurrency

37. 17 Sep 2002Embedded Seminar37 Reducing Memory Power Reduce memory accesses All compiler techniques for reducing cache misses Use registers Memory reference compaction Power aware page allocation Group active pages together

38. 17 Sep 2002Embedded Seminar38 Reducing Peripheral Power Communication Different power modes for communicating devices Data compression Adaptation in view of traffic and power Disk Spin-down and different power modes (when?) Display

39. 17 Sep 2002Embedded Seminar39 Summary Some research opportunities still exist Especially in algorithms and operating systems An integrated approach is needed All levels of the system cooperating with one another