1. Adders and Multipliers Review

2. ARITHMETIC CIRCUITS Is a combinational circuit that performs arithmetic operations, e.g. –Addition –Subtraction –Multiplication –Division with numbers in binary form.

3. Half Adder Generates the sum of 2 binary digits. X Y Sum = X  Y Cy = X.Y

4. Truth Table of Half Adder

5. Logic Diagram of Half Adder

6. Full Adder Forms the arithmetic sum of 3 input bits. X Y Sum = X  Y  Z Cout = X.Y + Z (X  Y) Cin

7. Truth Table of Full Adder

8. K-Maps for Full Adder

9. Full Adder A Full Adder can also be implemented using 2 HALF ADDERS and one OR gate. –Cascade two half adders (Array method)

10. Full Adder (Array Method)

11. Lab 3 : Multiplier Overview

12. 2-bits x 2-bits Multiplier

13. Terms 2 X 3 -------------- 6 Mutiplicand Multiplier Product

14. Multiplication in binary form? 1.Rewrite the multiplication in binary form. 2.Sketch the black box view. 3.The multiplier multiplies two __?__ bits numbers.

15. 2-bits x 2-bits Multiplier Design Two techniques: –Using the standard K-Map –Using Arrays (cascaded approach)

16. Part A: Using the K-Map Technique Sketch the back box. Sketch the Truth Table for a 2-bit “multiplier” and 2-bit “multiplicand”. –Input (Multiplier) = A1 and A0 –Input (Multiplicand) = B1 and B0 –Output (4-bits) = S3, S2, S1 and S0 or S[3..0] Using K-Maps, obtain the boolean expression for each output. Sketch the schematic diagram.

17. Lab 3 Requirement Simulate your design –Input A1 and A0 = counting sequence. –Input B1 and B0 = a fixed value. Study this waveform

18. LAb 3 Transfer in Max+Plus II using the Graphic Editor. Verify your design. Submit : Truth Table, K-Maps, Boolean Expressions, Printed: Schematic and Waveform results

19. Part B: Using the Array (Cascaded) Technique Create the 2x2 multiplier using Full ADDERS.

20. … tHE cONcEpt A1 A0 B1 B0 x A1B0 A0B0 A1B1 A0B1 + S0S1 S2S3 C C

21. A 2-Bit by 2-Bit Binary Multiplier

22. AND computes A 0 B 0 Half adder computes sum. Will need FA for larger multiplier.

23. In Lab 3 … Simulate your design –Input A1 and A0 = counting sequence. –Input B1 and B0 = a fixed value.

24. … in LAb 3 Transfer in Max+Plus II using the Graphic Editor. Verify your design. Submit : Truth Table, K-Maps, Boolean Expressions, Printed: Schematic and Waveform results

25. Part C: 4-bits x 4-bits Multiplier Using Array 2x2

26. Basic Idea of a Larger Multiplier (4-bits by 3-bits)

27. Multiplier Product The product of m-bit x n-bit numbers is an (m+n)-bit number. => The product of two 4-bit numbers is an 8-bit number.

28. How about this one? 13 X 11 -------------- 143 Mutiplicand Multiplier Product

29. 1101 (13) multiplicand X1011 (11) multiplier 1101 1101 0000 1101 10001111 (143) Product Partial products

30. A3A3 A2A2 A1A1 A0A0 B3B3 B2B2 B1B1 B0B0 A3B0A3B0 A2B0A2B0 A1B0A1B0 A0B0A0B0 A3B1A3B1 A2B1A2B1 A1B1A1B1 A0B1A0B1 A3B2A3B2 A2B2A2B2 A1B2A1B2 A0B2A0B2 A3B3A3B3 A2B3A2B3 A1B3A1B3 A0B3A0B3 S7S7 S6S6 S5S5 S4S4 S3S3 S2S2 S1S1 S0S0

31. From the previous slide: 1.The multiplier multiplies two __?__ bits numbers. 2.Sketch the black box view.

32. In Lab 3 Design a 4-bits x 4-bits multiplier using the Array (cascaded) technique, by utilizing: –The 2-bits x 2-bits Multiplier and full adder designed earlier. Hints : Look back at the concept of 2x2 multiplier. Take the same step.

33. … in LAb 3 Transfer in Max+Plus II using the Graphic Editor. Verify your design. Submit (Printed) - Schematic, and Waveform results

35. 4x4 Combinational Multiplier Note use of parallel carry-outs to form higher order sums 12 Adders, if full adders, this is 6 gates each = 72 gates 16 gates form the partial products total = 88 gates!

36. Array Multiplier 4 x 4 array of building blocks 1 building block

37. Extra Lab Activity Modify your design so that the output of your multiplier could be observed on two 7-segment displays on the UP2 board. Download your 4-bits x 4-bits multiplier design to the UP2 board.

38. Part C : 4 x 4 Multiplier Extra Activity Download your 4x4 multiplier to UP2 board using FPGA (Flex10K) 4x4 Multiplier (your design) Tenth & Unit Segment Decoder 7447 BCD to 7Seg 7447 BCD to 7Seg a - g A0 A1 A2 A3 B0 B1 B2 B3 Pin Configuration to input (use flex switch 1-8) Pin Configuration to output (use flex digit 1 & 2 )

39. Max+PlusII Tips Bus line A3 A2 A1 A0 A[3..0]

40. ~ GOOD UCK !!