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Department of Computer Engineering Tallinn University of Technology Estonia 8 th European Workshop on Microelectronics Education – EWME‘2010 Darmstadt,

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Presentation on theme: "Department of Computer Engineering Tallinn University of Technology Estonia 8 th European Workshop on Microelectronics Education – EWME‘2010 Darmstadt,"— Presentation transcript:

1 Department of Computer Engineering Tallinn University of Technology Estonia 8 th European Workshop on Microelectronics Education – EWME‘2010 Darmstadt, May 10-12, 2010 E-Learning Environment for WEB-Based Study of Testing R.Ubar 1, A.Jutman 1, J.Raik 1, S.Kostin 1, H.-D.Wuttke 2 1 Dept. of Computer Engineering Tallinn University of Technology Estonia 2 Dept. of Technical Informatics Technical University of Ilmenau Germany

2 E-Learning Environment for WEB-Based Study of Testing EWME May 10–12, 2010 2 Motivation ITRS: semiconductor test is already one of key problems in current generation of VLSI chips and its importance will be growing There is a strong demand for well-educated specialists in the area of IC and microelectronics testing Interactive training tools as addendum to LMS are needed to facilitate teaching process TUT has a 15 years tradition in developing training tools in microelectronic testing Students develop the software themselves under supervision of graduate students and senior personnel

3 8th European Workshop on Microelectronics Education – EWME‘2010 3 Motivation Cutting Edge Research − Needs custom developed algorithms and/or tools PhD Students − Need to run their experiments Undergraduate Students − Need introduction to the topic Department − Needs training materials and research

4 8th European Workshop on Microelectronics Education – EWME‘2010 4 Outline Different layers of the platform HW tools PC-based tools Web interface E-Learning tools Conclusions and discussion

5 8th European Workshop on Microelectronics Education – EWME‘2010 5 Different layers of the platform Web Tools PC Tools Hardware Tools

6 8th European Workshop on Microelectronics Education – EWME‘2010 6 Main components of the platform DefSim - an integrated measurement environment for physical defect study in CMOS circuits. TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability Web-based runtime interface for remote access to our tools Java applets – illustrative e-learning software written specifically for the web Other tools

7 8th European Workshop on Microelectronics Education – EWME‘2010 7 Different layers of the platform Web Tools PC Tools Hardware Tools

8 8th European Workshop on Microelectronics Education – EWME‘2010 8 Defect Study using DefSim DefSim is an integrated circuit (ASIC) and a measurement equipmrnt for experimental study of CMOS defects. The central element of the DefSim equipment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits. The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and I DDQ testing. http://www.defsim.com

9 8th European Workshop on Microelectronics Education – EWME‘2010 9 − Standard industrial CMOS technology − Area 19.90 mm 2 − Approx. 48000 transistors − 62 pins − JLCC68 package A built-in current monitor for I DDQ testing is implemented in each block. DefSim IC details

10 8th European Workshop on Microelectronics Education – EWME‘2010 10 NAND2 cell with floating gate VDD GND Q A B X Implementation of defects

11 8th European Workshop on Microelectronics Education – EWME‘2010 11 VDD GND Q A B NAND2 cell with D-S short (missing poly) Altogether there are over 500 different defects on the chip Implemented defects are shorts and opens in metal and poly layers To be close to the silicon reality each cell is loaded and driven by standard non-inverting buffers Implementation of defects

12 8th European Workshop on Microelectronics Education – EWME‘2010 12 DefSim in the classroom With DefSim you can Observe the truth table of correct circuit Observe the truth table of defective circuit Obtain defect/fault tables for all specific defects Define test patterns automatically or manually Activate IDDQ and voltage measurements Study behavior of bridging and open faults Study and compare different fault models

13 8th European Workshop on Microelectronics Education – EWME‘2010 13 “Plug and Play” – dedicated hardware and software DefSim lab environment

14 8th European Workshop on Microelectronics Education – EWME‘2010 14 Different layers of the platform Web Tools PC Tools Hardware Tools

15 8th European Workshop on Microelectronics Education – EWME‘2010 15 Used in 100+ institutions in 40+ countries Design Error Diagnosis Test Generators BIST Emulator Design Test Set Fault Table Test Set Optimizer Faulty Area Logic Simulator Defect Library Hazard Analysis Data Specifi- cation Multivalued Simulator Fault Simulator http://www.pld.ttu.ee/tt PC-Based Toolkit – Turbo Tester

16 8th European Workshop on Microelectronics Education – EWME‘2010 16 Used in 100+ institutions in 40+ countries Design Error Diagnosis Test Generators BIST Emulator Design Test Set Levels: Gate Macro RTL Fault Table Test Set Optimizer Methods: BILBO CSTP Hybrid Faulty Area Circuits: Combinational Sequential Logic Simulator Formats: EDIF AGM Defect Library Hazard Analysis Data Specifi- cation Algorithms: Deterministic Random Genetic Multivalued Simulator Fault models: Stuck-at faults Physical defects Fault Simulator http://www.pld.ttu.ee/tt PC-Based Toolkit – Turbo Tester

17 8th European Workshop on Microelectronics Education – EWME‘2010 17 Freeware Freeware Downloadable via the Web Downloadable via the Web Windows, Linux, UNIX/Solaris Windows, Linux, UNIX/Solaris EDIF design interface EDIF design interface ATPGs, BIST, simulators, test compaction ATPGs, BIST, simulators, test compaction Provides homogeneous environment for research and training Provides homogeneous environment for research and training Turbo Tester: Basic Facts

18 8th European Workshop on Microelectronics Education – EWME‘2010 18 Different layers of the platform Web Tools PC Tools Hardware Tools

19 8th European Workshop on Microelectronics Education – EWME‘2010 19 BIST Analyzer: covered topics Test Pattern Generators (PRPG): − LFSR − Modular LFSR − Cellular Automata − GLFSR − Weighted TPG − etc. Combined Techniques (PRPG + Memory): − Reseeding − Multiple polynomial BIST − Hybrid BIST − Bit-Flipping BIST − Column matching BIST − etc. BIST Control Unit Circuit Under Test (CUT) Test Pattern Generator (PRPG)........ Output Response Analyzer (MISR) BIST Memory Typical BIST Architecture

20 8th European Workshop on Microelectronics Education – EWME‘2010 20 Embedded generators (PRPG) and their properties PRPG optimization methodologies and algorithms Combined BIST solutions (PRPG+memory) Fault detection and diagnosis in BIST BIST Analyzer: covered topics

21 8th European Workshop on Microelectronics Education – EWME‘2010 21 BIST Analyzer

22 8th European Workshop on Microelectronics Education – EWME‘2010 22 BIST Analyzer

23 8th European Workshop on Microelectronics Education – EWME‘2010 23 Different layers of the platform Web Tools PC Tools Hardware Tools

24 8th European Workshop on Microelectronics Education – EWME‘2010 24 Web Interface

25 8th European Workshop on Microelectronics Education – EWME‘2010 25 Different layers of the platform Web Tools PC Tools Hardware Tools

26 8th European Workshop on Microelectronics Education – EWME‘2010 26 E-Learning software on DFT http://www.pld.ttu.ee/applets

27 8th European Workshop on Microelectronics Education – EWME‘2010 27 Essential supplement to the university lectures Accessibility over Internet Visual content (“Living Pictures”) Comprehensive examples Better organization of teaching materials Based on free educational software Distance learning & computer aided teaching Easy to implement in other universities Constantly updated Benefits of e-learning software

28 8th European Workshop on Microelectronics Education – EWME‘2010 28 Test Generation Error Diagnosis Built-In Self-Test Design for Testability Test and Diagnostics RTL Design and Test Boundary Scan Applet on Basics of Test & Diagnostics Applet on RTL Design and Test Applet on Boundary Scan Standard Schematic & DD Editor Turbo Tester Group of Applets on Control Part Decomposition E-Learning Software Java Applets Turbo Tester Scenario 4 Design for Testability Scenario 3 Built-InSelf-Test Scenario 2 ErrorDiagnosis Scenario 1 TestGeneration Scenario 4 Design for Testability Scenario 3 Built-InSelf-Test Scenario 2 ErrorDiagnosis Scenario 1 TestGeneration Supporting Materials Learning Scenarios Web based tools for classroom, home and exams Tools for laboratory research

29 8th European Workshop on Microelectronics Education – EWME‘2010 29 E-Learning Software Logic level diagnostics System level test & DfT Software for classroom, home, labs and exams: http://www.pld.ttu.ee/applets Boundary Scan

30 8th European Workshop on Microelectronics Education – EWME‘2010 30 manual test pattern generation assisted by the applet generation of pseudo-random test vectors by LFSR fault simulation & study of fault table combinational fault diagnosis using fault tables sequential fault diagnosis by guided probing Applet on basics of test

31 8th European Workshop on Microelectronics Education – EWME‘2010 31 design of a data path and control path (microprogram) on RT level investigation of tradeoffs between speed of the system & HW cost RT-level simulation and validation gate-level deterministic test generation and functional testing fault simulation logic and circular BIST, functional BIST, etc. design for testability Applet on RT-level design and test

32 8th European Workshop on Microelectronics Education – EWME‘2010 32 Simulation of operation of TAP ControllerSimulation of operation of TAP Controller Illustration of work of BS registersIllustration of work of BS registers Insertion and diagnosis of interconnection faultsInsertion and diagnosis of interconnection faults Design/editing of BS structures using the BSDL languageDesign/editing of BS structures using the BSDL language Design/description of the target board using several chipsDesign/description of the target board using several chips Applet on Boundary Scan

33 8th European Workshop on Microelectronics Education – EWME‘2010 33 An applet targeted at binding all the applets and the Turbo Tester Supportedinterface formats are: AGMDWGVHDLGIFEDIF?PostScript? Design for Testability Applet on Basics of Test & Diagnostics Applet on RTL Design and Test Applet on Boundary Scan Standard Schematic & DD Editor AGM, DWG AGM, GIF AGM AGM,GIF Main functions of the applet are: gate-level schematic editor gate-level schematic editor SSBDD editor SSBDD editor schematic ↔ SSBDD on-the-fly schematic ↔ SSBDD on-the-fly converter converter different format reader/converter different format reader/converter Schematic and DD editor

34 8th European Workshop on Microelectronics Education – EWME‘2010 34 Design Specification Design Implementation Test Vector File Verification Results XTimport Tool ATPG Circuit Schematic Human Being Diagnostic Vectors Report File Prediag Tool Verification Tool Circuit Netlist Intermediate Diagnosis Vecmanager Tool Final Diagnosis Turbo Tester tools and formats Other Example of a lab work scenario

35 8th European Workshop on Microelectronics Education – EWME‘2010 35 Conclusions The main features of the platform: Research engine + training software Layered structure HW and SW components Remote access Distance learning and e-learning Computer-aided teaching Freeware

36 8th European Workshop on Microelectronics Education – EWME‘2010 36 Conclusions

37 8th European Workshop on Microelectronics Education – EWME‘2010 37 Our Tools on the Web The Turbo Tester home page http://www.pld.ttu.ee/tt/ The Turbo Tester web-server page http://www.pld.ttu.ee/webtt/ DefSim home page http://www.defsim.com Java applets home page http://www.pld.ttu.ee/applets/

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