1. FPGA Fault Emulator Jiří Kvasnička, Pavel Kubalík, Hana Kubátová

2. Purpose of FPGA Fault Emulator Observe the SEU resistance of the design mapped in FPGA (with regard to the bitstream utilization) The SEU is emulated by 1-bit change in the bitstream Evaluation of Fault Security (FS), Self Testing (ST) and Totally Self-Checking (TSC) properties Evaluation of dependability parameters for practical application

3. Hardware Realization AT94K40AL FPSLIC (FPGA+AVR) Two copies of benchmark present: tested and “golden” Exhaustive test generator and fault class evaluation logic AVR controls the testing and reconfiguration Bitstream analysis and area selection are performed in PC.

4. Used fault classification A: Hidden fault (The result is always OK) B: Detected fault (wrong result always detected by CED) C: Undetected fault  (result is wrong, but never detected by CED) D: Temporarily detected fault  (The wrong result is sometimes detected by CED and sometimes is not) Further Fault security (A or B), Self Testing (B or D) and Totally Self-checking (B) parameters computation

5. Testing area

6. Results I (LUTs) More hidden faults (A category) Other categories are comparable

7. Results II (LUTs, HW / SW comparison )

8. Tested bits range Presented results: LUT (11% of whole bst) Current progressing state: LUT, Cell configuration and Cell connection to Bus

9. Most recent result

10. Result interpretation problem Different count of fault in SW simulation and HW emulation (comparable?) Result depends on place&route tool (another way throw mapping gives different results) Inconsistency of a few bits in cell interconnection (sometimes giving different result) Testing of complete chip area results in many undetectable faults (it has a relation to the usage of the FPGA chip) – testing only used bits

11. Conclusions + Some results from circuit mapped in the FPGA + Some results from circuit mapped in the FPGA – FPGA structure and bitstream knowledge required – FPGA structure and bitstream knowledge required – Result is affected by place and route process – Advantage of testing speedup (with comparison with software simulation) is degraded by time needed for Place&route and programming – Advantage of testing speedup (with comparison with software simulation) is degraded by time needed for Place&route and programming