1. Global Trigger H. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, J. Strauss, A. Taurok, C.-E. Wulz Vienna Group presented by Claudia-Elisabeth Wulz Trigger Meeting, CERN, 17 Sep 2003

2. Trigger Meeting, Sep. 2003 C.-E. Wulz2 Global Trigger Rack

3. Trigger Meeting, Sep. 2003 C.-E. Wulz3 All boards on front side. Boards arranged for minimum cable length. Global Trigger Crate

4. Trigger Meeting, Sep. 2003 C.-E. Wulz4 VME interface PSB GTL6U GTL_CONV Global Trigger Prototype Crate

5. Trigger Meeting, Sep. 2003 C.-E. Wulz5 VME interface MEMORY SYNC chips ROP for DAQ Input module Synchronisation and monitoring of trigger data PSB6U only for the Prototype Crate PSB-6U Prototype Board

6. Trigger Meeting, Sep. 2003 C.-E. Wulz6 40, 80 MHz CLK drivers DS92LV16 receivers Registers for 40  80 MHz conversion Infiniband connectors DS92LV16 transmitter for tests new PSB_IN80 for PSB-6U

7. Trigger Meeting, Sep. 2003 C.-E. Wulz7 VME interface CONV chips 80MHz GTL+ signals Channel LinkRec +1.5V supply VME to GTL6U GTL_CONV is used only in the Prototype Crate Channel Link signals GTL Conversion Board

8. Trigger Meeting, Sep. 2003 C.-E. Wulz8 Calculates 64 trigger algorithms GTL6U will be used in the prototype crate as well as in the final GT-crate GTL-6U Logic Board (right side) VME REC chips COND chips GTL+ signals 4x4 calo objects 4 muons

9. Trigger Meeting, Sep. 2003 C.-E. Wulz9 TIM chip TTCrx CLOCK circuits LVDS drivers CLK, BCRES, L1A, RESET to each VME slot VME TIM-6U will be used in the prototype as well as in the final GT and DTTF crates. Front Panel new TIM-6U Timing Module

10. Trigger Meeting, Sep. 2003 C.-E. Wulz10 A.T. 21.2.03 FDL-9U Final Decision Logic VME ALGO bits to DAQ ALGO bits to EVM Final OR bits to TCS Techn.Trigger bits from PSB ALGO bits from GTL FDL chip on MEZZ896

11. Trigger Meeting, Sep. 2003 C.-E. Wulz11 TCS-9U Central Trigger Control Board VME FastSigs 24 part‘s + 8DAQ part‘s TCS status to 8 DAQ part‘s L1A,... to 32 TTCvi FastSigs from 8 Emulators TCS_MON chip TCS chipClock EVM+DAQ records

12. Trigger Meeting, Sep. 2003 C.-E. Wulz12 bottom side top side 50 Ohm connectors XC2V2000-4FF896C BGA: 1mm pitch, track width=83  m Mezzanine Board (MEZZ896) MEZZ896 will be used in TCS-9U and FDL-9U

13. Trigger Meeting, Sep. 2003 C.-E. Wulz13 GCT/GT integration test setup Bristol + Vienna groups, Vienna, July 2003

14. Trigger Meeting, Sep. 2003 C.-E. Wulz14 GCT/GT integration test results and plans Link latency 50 ns with 1m cable, 65 ns with 5m cable. Data exchange 64 bits per 25 ns sent over one two-pair Infiniband cable. Different sets of patterns have been programmed at the transmitter end of the link and successfully read from a memory on the PSB. Clock PLL-based clock drivers to stabilize the TTC clock signals can be used. Long term stability Full test still to be made. 20000 LHC orbits equivalent to 5. 10 9 bit cycles tested. Further tests Planned in Vienna with boards from Bristol in autumn 2003.

15. Trigger Meeting, Sep. 2003 C.-E. Wulz15 GT on-line and ORCA software C++ test programs exist to run the following boards both stand-alone and as a system : PSB-6U, GTL-CONV, GTL-6U, TIM-6U, TTCvi. The programs are being implemented as XDAQ-plugins. The GT setup definition is planned in.xml format, also to be used by ORCA. We are working on the SETUP program, including on a concept with a GUI.

16. Trigger Meeting, Sep. 2003 C.-E. Wulz16 Milestones updated Custom Backplane for VME 9U crate 4 6U Prototype: Channel Links... existsMS 03/02 –9U Backplane: 80MHz GTLp and Channel Links,... design in progressMS 03/03  09/03  12/03 PSB Input board (synchronisation, monitoring) 4 6 channel 6U Prototype: Channel Link receivers... board testedMS 03/02 4 PSB-IN80: DS92LV16 serial receivers... board tested –12 channel board: memories inside FPGAs...conceptual design MS 06/04 GTL Logic board: 4 Conversion board for prototype... board testedMS 03/02 –GTL-6U prototype: 20 channels …hardware is testedMS 06/03 Signal transfer tested with test patterns -> ok… working on firmware XDAQ compatible test program in C++ exists Loading of conditions not tested yet (software under development) –GTL-9U board: 32 channels...conceptual design MS 11/04 4 , 4 isol. e/ , 4e/ , 4 central jets, 4 fwd jets, 4  -jets,  E T, E T mis, H T, 12 jet counts TIM Timing board... board tested MS 06/03  09/04 4 6U size, TTCrx, clock and L1A distribution, also used by DTTF; working on version for new TTCrx MEZZ896 4 Mezzanine boards (used on TCS-9U, FDL-9U)... boards produced MS 06/03 FDL-9U Final Decision board... design in progress MS 06/03  11/03  02/04 TCS-9U Central Trigger Control board... Layout finished MS 04/03  09/03  12/03 GTFE-9U Readout board... conceptual design MS 12/03  03/04  02/05 Global Trigger Status and Milestones Sept. 2003

17. Trigger Meeting, Sep. 2003 C.-E. Wulz17 Production, Full Chain and Slice Tests, Integration GTL-6U  hardware ok TIM-6U  09/04 (version for new TTCrx) TCS-9U  09/03  12/03 BACK-9U  09/03  12/03 FDL-9U  11/03  02/04 System test (full chain) of 20-channel GT (without GTFE)  06/04 GT system tests  6/05 Global Trigger PSB-9U  06/04 Integration of GT/GMT with DAQ  01/06 Slice tests performed in Vienna as boards become available. Installation and commissioning in USC55 planned in phase with other subsystems (GCT, regional muon trigger systems) during second half of 2005. GTFE  03/04  02/05 GTL-9U  11/04 Global Muon Trigger FPGA design  12/03 Board production  06/04 GMT system tests  01/05 Global Trigger PROTOTYPE BACK-6Uok PSB-6U ok PSB-IN80 ok GTL-CONVok GTL-6U hardware tested (Milestone 6/03) TIM-6U done (Milestone 6/03) - prototype will be used as spare module for final system Integration test with GCTdone (July 2003)

18. Trigger Meeting, Sep. 2003 C.-E. Wulz18 Conclusions GTL-6U Logic board produced and tested TIM-6U Timing module produced and tested TCS-9U Layout of TCS module finished FDL-9U Final Decision Logic is in progress PSB_IN80, GTL_CONV, MEZZ896 Auxiliary boards produced and tested XDAQ compatible on-line software is under development ORCA software is being updated