1. PS - Theo Claasen DAC 2000 - 1 First-time-right silicon, but…. to the right specification Theo A.C.M. Claasen Chief Technology Officer Philips Semiconductors

2. PS - Theo Claasen DAC 2000 - 2 Content Consumer systems as driver of design technology The design crisis and its solution: reuse Generations of reuse How to get the specifications right before making the chip –Rapid silicon prototyping Conclusions

3. PS - Theo Claasen DAC 2000 - 3 (R)evolution in the consumer market Consumer systems become –Digital –Programmable (downloadable) –User adaptive –Connected (with each other and to a network) –Multifunctional fashion items

4. PS - Theo Claasen DAC 2000 - 4 Example

5. PS - Theo Claasen DAC 2000 - 5 The environment Same functions wanted –At home –On the move –In the office All the time, anywhere With consistency of –Data –User interface

6. PS - Theo Claasen DAC 2000 - 6 Consequences for design IC design needs to handle –Integrated systems (SoC) –Increasing complexity –Fast time to market (too late = no business) –Hardware and software –High processing speed and / or low power This requires a design process that is –Predictable in time and performance –Efficient The key elements of such a design process are –High level of re-use –Silicon prototyping So what about the design crisis?

7. PS - Theo Claasen DAC 2000 - 7 Design crisis Process technology provides a 59% per year increase of complexity (Moore’s law) Design efficiency increases by “only” 25% per year Log # transistors Time Technology 59% / year Design 25% / year Design gap

8. PS - Theo Claasen DAC 2000 - 8 Design crisis revisited The design gap has been predicted for the last two decades Yet, in every new technology, we design chips of 1 cm 2 that are completely utilized Log # transistors Time Technology 59% / year average Design 25% / year & paradigm shifts New reuse method New process technology

9. PS - Theo Claasen DAC 2000 - 9 Reuse Reuse comes in generations

10. PS - Theo Claasen DAC 2000 - 10 Conditions for reuse A consistent methodology –Standards Interconnection of elements File and directory structure Test –Guidelines Design (power, clock) Test Debug CoReUse ® standards CoReUse ® constraints Wrapping of a coreContents of a core Directory structure All views present & consistent File name conventions All soft, firm or hard rules Previous + all maintenance rules All CoReUse ® guidelines

11. PS - Theo Claasen DAC 2000 - 11 Conditions for reuse A consistent methodology A comprehensive library of reuse elements –Compliant with the methodology –Proven on silicon (individually and in combination)

12. PS - Theo Claasen DAC 2000 - 12 Conditions for reuse A consistent methodology A comprehensive library of reuse elements Development tools Rapid silicon prototyping

13. PS - Theo Claasen DAC 2000 - 13 Rapid silicon prototyping It is no use to have “first-time-right” silicon if it was not designed with the right specification Specifications can only be right after extensive simulation –With real data –In a real environment Simulation –Needs to be bit-accurate –Should comprise hours of data (at 100Mhz = 4.10 11 cycles) –Debugs both hardware and software The only simulation that is fast enough is using silicon –Running at (almost) same speed –Having one-to-one mapping to actual silicon

14. PS - Theo Claasen DAC 2000 - 14 Rapid silicon prototyping Design cycle benefits RSP Design Process Production Release Conventional Design Process (1 st time right Si) Production Release SW Development and Validation Silicon Fabrication HW Development and Validation Placement, Routing & Physical Verification Faster chip development –More than 50% total design cycle reduction –True HW / SW co-development Higher probability of first-pass success

15. PS - Theo Claasen DAC 2000 - 15 Management attention –Understanding of the benefits –Organization –Discipline –Rewards (for creation and usage) Conditions for reuse A consistent methodology A comprehensive library of reuse elements Development tools Rapid silicon prototyping

16. PS - Theo Claasen DAC 2000 - 16 Service –Support organization (help desk) –Documentation –Communication Conditions for reuse A consistent methodology A comprehensive library of reuse elements Development tools Rapid silicon prototyping Management attention

17. PS - Theo Claasen DAC 2000 - 17 The first generation reuse Standard cells Has been relatively easy –Extensive libraries for each technology generation Very successful after emergence of logic synthesis tools Various forms of RSP available –FPGA’s –HW simulation

18. PS - Theo Claasen DAC 2000 - 18 Standard cells

19. PS - Theo Claasen DAC 2000 - 19 The second generation reuse IP blocks (virtual components ) Virtual components have been around for some time Limited success so far, except for specific blocks –CPU cores –DSP cores –Memories –Some periphery devices Major problems –Slow emergence of standards (VSIA) –Business models and liabilities (VCX) –Rapid silicon prototyping –Support and service Extension to SW reusable modules needed –Speeding up HW design brings SW on critical path

20. PS - Theo Claasen DAC 2000 - 20 IP reuse Sea-of-IP 

21. PS - Theo Claasen DAC 2000 - 21

22. PS - Theo Claasen DAC 2000 - 22 IP based RSP Reference Design Deconfigurable & Extendible Prototype Chip Made from Reusable Components PS own IP 3 rd Party IP Customer IP The busses, not the CPU, are the backbone of this strategy Prototype to finished ASIC added (integrated) modified (extended) removed (deconfigured) Production ASIC Deconfigured & Extended Customer Specific Solution

23. PS - Theo Claasen DAC 2000 - 23 VLSI Velocity TM The RSP7 board and development system From system-on-a-benchtop to system-on-a-chip –Wealth of development functionality supporting system, chip and software development Logic Analyzer HW Emulator Standard Plug-in Board On-Board GateField FPGA JTAG Control JumpStart ARM Host Compiler & Debugger Velocity™ Rapid Silicon Prototyping System User Interface FPGA Proto Board

24. PS - Theo Claasen DAC 2000 - 24 Logic Analyzer HW Emulator FPGA Proto Board Standard Plug-in Board JumpStart ARM Host Compiler & Debugger User Interface On-Board GateField FPGA JTAG Control Velocity™ Rapid Silicon Prototyping System

25. PS - Theo Claasen DAC 2000 - 25 The third generation reuse Architectures (Silicon System Platform) Silicon System Platform –Flexible architecture for hardware and software –Specific (programmable) components –Bus architecture –Software modules –Rules and guidelines for design of HW and SW Has been successful in PC’s –Dominance of a few players who specify and control architecture Application domain specific (difference in constraints) –Speed (compute power) –Dissipation –Costs –Real / non-real time data

26. PS - Theo Claasen DAC 2000 - 26 Architecture reuse System DSP ON-CHIP BUSES CPUDRAMAnalog Firmware Different Systems-on-Silicon Platform DSP core CPU core bus Memory Specific blocks OS API Applications Drivers One platform per application domain

27. PS - Theo Claasen DAC 2000 - 27 Architecture reuse

28. PS - Theo Claasen DAC 2000 - 28 Nexperia TM Application domain specific (e.g. digital video, digital audio, telecom handsets) architectural concept for programmable functions, comprising –Processors (CPU for control and DSP for streaming data) –Connected with low-speed and high-speed busses to a shared memory –A comprehensive set of peripherals –Software components ranging from drivers and API to application modules Scalable from high end to low end –Cost –Performance –Features

29. PS - Theo Claasen DAC 2000 - 29 TM-xxxx D$ I$ TriMedia CPU DEVICE I/P BLOCK...... DVP System Silicon VLIW Media Processor: 100 to 300+ MHz 32-bit or 64-bit Nexperia System Busses PI bus Memory bus 32-128 bit PI BUS SDRAM MMI DVP MEMORY BUS DEVICE I/P BLOCK PRxxxx D$ I$ MIPS CPU DEVICE I/P BLOCK...... PI BUS General Purpose RISC Processor 50 to 300+ MHz 32-bit or 64-bit Library of Device Blocks Image coprocessors DSPs UART 1394 USB … and more TriMedia TM MIPS TM Nexperia TM DVP Hardware architecture Flexible architecture for digital video applications

30. PS - Theo Claasen DAC 2000 - 30 Nexperia TM Scalability VLIW SDRAM MMI TriMedia CPU + Device blocks when control functions are minimal MIPS CPU + Trimedia CPU replacing some Device blocks RISC SDRAM VLIW MMI Single architecture, multiple product configurations –Processor core options - TM32, TM64, MIPS32, MIPS64... –Device block options Highly programmable to weakly programmable MIPS CPU + Device blocks + Software RISC SDRAM MMI

31. PS - Theo Claasen DAC 2000 - 31 NAPA Nexperia TM Advanced Prototyping Architecture

32. PS - Theo Claasen DAC 2000 - 32 NAPA Nexperia TM Advanced Prototyping Architecture Is the next generation Rapid Silicon Prototyping –Expands on the capabilities of Velocity™ –Builds nicely on the platform architecture Allows mix and match of processors and peripherals –Upgrading the processor(s) –Upgrading the peripherals –Independently

33. PS - Theo Claasen DAC 2000 - 33 The NAPA system Start with a platform architecture with two processors (a CPU and a DSP) and a memory controller. Add a high speed bus to accommodate a high speed memory interface for streaming data. DMA Gate MM/S DMA Gate M/SM MM MM Peripheral M/S MEMC Processor Periph Processor Periph Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Crossover Bridge M/S Bridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S

34. PS - Theo Claasen DAC 2000 - 34 MEMC Processor Periph Tunnel MEMC Processor Periph Tunnel Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S BridgeTunnelBridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge (optional) Split the system into logical parts by using bridges and tunnels Bridge: no latency modest speed Tunnel: some latency high speed In many systems one of the memory controllers will be disabled The NAPA system

35. PS - Theo Claasen DAC 2000 - 35 The NAPA system MEMC Processor Periph Tunnel For each of these parts a prototype chip is made MEMC Processor Periph Tunnel Separate boards for processor and memory and for periphery Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S Bridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Tunnel Bridge Peripherals CPUs/Memory

36. PS - Theo Claasen DAC 2000 - 36 NAPA card cage CPUs/Memory Peripherals FPGA card Backplane allows probing and logic analyzer connections Cards can be inserted in any order

37. PS - Theo Claasen DAC 2000 - 37 MEMC Processor Periph Tunnel MEMC Processor Periph Tunnel Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S BridgeTunnelBridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge Building an IC from the prototype ASIC or CSIC MEMC Processor Periph Tunnel MEMC Processor Periph Tunnel Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S BridgeTunnelBridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge Put it all together

38. PS - Theo Claasen DAC 2000 - 38 MEMC Processor Periph Tunnel MEMC Processor Periph Tunnel Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/SM Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S BridgeTunnelBridge Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge Building an IC Deconfigure: remove unwanted components MEMC Processor Periph Processor Periph Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge

39. PS - Theo Claasen DAC 2000 - 39 MEMC Processor Periph Processor Periph Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge Building an IC Extend: add prototyped (FPGA) components This will provide the database for the chip MEMC Processor Periph Processor Periph Peripheral MM/S Peripheral M/SM Peripheral M/S Peripheral M/S Peripheral MM/S Peripheral M/S DMA Gate MM/S DMA Gate M/SM Crossover Bridge M/S Peripheral M/S Peripheral M/S Peripheral M/S Peripheral M/S Bridge Peripheral M/S Peripheral MM/S Peripheral M/S Peripheral M/S

40. PS - Theo Claasen DAC 2000 - 40 The fourth generation reuse IC reuse We need to go to 100M+ transistor chips in deep sub-micron Mask costs get very expensive Too expensive to spin silicon –For correcting design errors –For correcting specification errors –For designing variants Basic technology: retargetable / reconfigurable systems No methodology yet A number of start ups develop technology

41. PS - Theo Claasen DAC 2000 - 41 IC reuse Problems to be addressed –Silicon efficiency (area) –Compiler efficiency (code size and speed) –Computational efficiency (speed) –HW / SW co-design –Reconfigurable interconnectivity –SW design for reuse No prototyping issues anymore Guaranteed fast time-to-market

42. PS - Theo Claasen DAC 2000 - 42 Conclusions Consumer IC’s generate the need for fast and efficient design methods The design efficiency increases slower than Moore’s law New generations of reuse technology are the solution to the corresponding design gap IP reuse is emerging The next wave will be architecture reuse (Silicon System Platforms) Rapid silicon prototyping is an essential element of these reuse technologies The new wave may be IC reuse with retargetable architectures