Presentation is loading. Please wait.

Presentation is loading. Please wait.

Emulator System for OTMB Firmware Development for Post-LS1 and Beyond Aysen Tatarinov Texas A&M University US CMS Endcap Muon Collaboration Meeting October.

Published byGervais Butler Modified over 9 years ago

Similar presentations

Presentation on theme: "Emulator System for OTMB Firmware Development for Post-LS1 and Beyond Aysen Tatarinov Texas A&M University US CMS Endcap Muon Collaboration Meeting October."— Presentation transcript:

1 Emulator System for OTMB Firmware Development for Post-LS1 and Beyond Aysen Tatarinov Texas A&M University US CMS Endcap Muon Collaboration Meeting October 1, 2013

2 Outline OTMB firmware development for post-LS1 – Emulator system – Setup & data formats OTMB firmware development for beyond LS1 – GEM detectors – Additional data formats Tasks and milestones Conclusions 2

3 Emulator of CSC Data CSC DCFEB ALCT OTMBL1 Muon Trigger Emulator Board DCFEB ALCT OTMB Emulator system for OTMB firmware development: —Dedicated emulator board to emulate data coming from CSC to OTMB Start with emulation of DCFEB comparator data Later add emulation of ALCT data (several options being considered) 3

4 Test Stand @ TAMU Emulator board to be used at current ME1/1 electronics test stand at TAMU VME peripheral crate with – OTMB – CCB (provides clocking for all boards) – VME Controller 4

5 TAMU responsibility: R&D of new TMB Mezzanine Boards TMB Mezz Board Prototype is a good candidate for the emulator board! (use Snap12 Fiber Transmitter to send CSC data) Where do we get the Emulator Board? Gigabit Ethernet Link (communication with PC) VIRTEX-6 FPGA Snap12 Fiber Transmitter Snap 12 Fiber Receiver Prototype TMB Mezzanine Board 5

6 PC with software which controls the test stand: – Data generation and loading into the emulator board: – Data transmission from the emulator board to OTMB – Readout of trigger results from OTMB Test Stand Setup PC with test stand control software Emulator BoardOTMB Gigabit Ethernet Data & Control Fiber links Readout & Control 6

7 Data generation and loading into the emulator board: – PC generates data to be transmitted to OTMB according to CSC data formats – PC uploads the data to memory units on the emulator board Test Stand Setup PC with test stand control software Emulator Board OTMB Gigabit Ethernet Data & Control Fiber links Readout & Control 7

8 Data transmission from the emulator board to OTMB: – A command from PC initiates data transmission – Emulator transmits data from specified memory units to OTMB through particular fiber links Test Stand Setup PC with test stand control software Emulator Board OTMB Gigabit Ethernet Data & Control Fiber links Readout & Control 8

9 Test Stand Setup PC with test stand control software Emulator Board OTMB Gigabit Ethernet Data & Control Fiber links Readout & Control Readout of trigger results from OTMB: – PC communicates with OTMB to readout information about triggered events 9

10 Trigger Algorithm in Hardware vs Software Control and understand OTMB trigger algorithm both in hardware and software by comparing trigger decisions in: – OTMB firmware – CMSSW trigger stubs emulator It should be possible to implement the readout of trigger results through ODMB in a format that could be used as input to CMSSW 10

11 7 DCFEBs (Digital Cathode Front End Boards) DCFEB Data Format Di-strips with no hits: all zero bits Di-strip with hit: hit location with half-strip precision encoded in “triads “ — 3 bits transmitted over 3 BXs – 1 st bit — tells there is a hit in this di-strip – 2 nd bit — tells in which strip there is a hit – 3 rd bit — tells in which half-strip there is a hit Each DCFEB: 6 layers * 8 di-strips = = 48 signals (bits) per BX 11

12 Emulator board FPGA: 256 memory pages (4KB each) – Group them into 7 memory units (36*4 = 144 KB each) – One memory unit represents one specific DCFEB – Emulate data stream from 7 DCFEBs = transmit data from memory units through 7 fiber links Each DCFEB: 48 bits per BX Single memory unit can store 144*1024*8/48 ~ 25000 BXs of data (well enough for any tests!) How much DCFEB data can we emulate? DCFEB1DCFEB2DCFEB3DCFEB4DCFEB5DCFEB6DCFEB7 12

13 Beyond LS1: GEM detectors GEMs to be installed during LS2 (and possibly LS3) – Redundancy to CSC in the very forward region, where especially high trigger rates expected in the near future GEM GE1/1 detector planned for LS2 CMS upgrade period (2018) Possible installation of a second GEM station (GE2/1) for LS3 CMS upgrade period GE1/1 GE2/1 13

14 Combined GEM-CSC Trigger Redundancy to CSC through combined GEM-CSC trigger Transmit GEM data to CSC OTMB through optohybrid board (provide data properly formatted for CSC TMB) – No changes in CSC scheme needed – Requires implementation of GEM-CSC trigger algorithm in OTMB firmware 14

15 Emulator of CSC and GEM Data CSC DCFEB ALCT GEM Optohybrid Board OTMBL1 Muon Trigger Add emulation of GEM data from optohybrid board Emulator Board DCFEB ALCT Optohybrid Board OTMB 15

16 GEM Data Format 3 columns 6, 8, 10 partitions VFAT3 chips GEM hit location encoding: Column (2 bits) Partition (3-4 bits) Pad (5-6 bits) Total: 10-12 bits (most likely 10 bits) GEM data to OTMB over 2 fiber links: 96 bits / BX Encode up to 9 GEM pad hits Negligible probability to have more than 9 hits per GEM chamber 16

17 Tasks and Milestones Three main task groups: Development of test stand control software Development of emulator board firmware Development of OTMB firmware 17

18 Tasks and Milestones 1. Development of test stand control software 1.1. Data loading into emulator board memory pages 1.1.1. Standalone program for generating and uploading arbitrary data DONE 1.1.1.1. Add XDAQ interface 1.1.2. Generate data according to CSC and GEM data formats 1.1.2.1 Generation of simple stub patterns (straight stub pattern, etc.) 1.1.2.2 Using data from simulation/real data that includes background as input 1.2. “Go” command initiating data transmission 1.3. Readout from OTMB 1.3.1. Readout last trigger results via VME 1.3.2. Readout trigger results via ODMB 18

19 Tasks and Milestones 2. Development of emulator board firmware 2.1. Data transmission from specific memory units to OTMB through specific fibers 2.1.1. Verify the fact of data transmission 2.1.1.1. LEDs and test signals on emulator board 2.1.1.2. Verify if memory units are empty after data transmission 2.1.2. Verify correctness of data transmission 2.1.2.1. Basic readout of last trigger from OTMB via VME 3. Development of OTMB firmware 3.1. Take over current OTMB firmware (UCLA firmware) 3.2. Implement ODMB readout 3.3. Implement post LS1 changes in CSC trigger 3.4. Implement GEM-CSC algorithm 19

20 Short Term Plans Short-term plan: proof the concept with simple options: – Software to generate CSC data describing one straight stub DCFEB data only, no ALCT and GEM data yet – Use standalone program to load into the emulator board Already implemented – Assign specific memory pages to specific fiber links, transmit the data to OTMB – Basic readout from OTMB to see if we can trigger the same stub Last trigger stub is already available with VME tools 20

21 Conclusions Emulator system for OTMB development: – Mezz board prototype as emulator board – ME1/1 electronics test stand at TAMU – Test stand control software Start with emulation of DCBEF data, later add emulation of ALCT and GEM data Emulator board has enough memory to store muon data of any arbitrary complexity Important tool for development and validation, study of efficiency and performance of both post-LS1 and beyond changes to OTMB firmware 21

22 BACKUP SLIDES 22

23 Muon Triggering in Forward Region No redundancy in the very forward region! Higher trigger rates and more hostile conditions expected in near future, especially in the forward region (PU ~20 in 2012, PU ~200 after LS2) 23

24 GEM Detectors GEM (Gaseous Electron Multiplication) detectors – Excellent spatial resolution and good timing at high rates Proposed installation: redundancy to CSC in the very forward region GEM GE1/1 detector planned for LS2 CMS upgrade period (2018) Possible installation of a second GEM station (GE2/1) for LS3 CMS upgrade period GE1/1 GE2/1 24

25 Muon Bending Angle GEM detectors to improve momentum resolution by measuring muon “bending angle” (CSC are too thin for it) View down from the top of the CMS Odd chambers Even chambers 25

26 Realistic Emulation in Test Stand Realistic emulation of CSC (GEM) electronics configuration and operating conditions during actual data taking – Same data formats and similar rates as in real operations – CSC and GEM hits: correlations in the locations differences in time arrival The stand will provide: – Test-bed for design and development, debugging and validation of the OTMB firmware (both for standalone CSC and GEM-CSC regimes) Important tool in developing firmware for the OTMB 26

Download ppt "Emulator System for OTMB Firmware Development for Post-LS1 and Beyond Aysen Tatarinov Texas A&M University US CMS Endcap Muon Collaboration Meeting October."

Similar presentations

TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)

TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)
Improvements to ME1/1 TMB Algorithm from Simulation Studies US CMS EMU Workshop 2013-10-01 Vadim Khotilovich, Texas A&M University.

Improvements to ME1/1 TMB Algorithm from Simulation Studies US CMS EMU Workshop Vadim Khotilovich, Texas A&M University.
Endcap Muon meeting: CMU, Oct 19, 2003 J. Hauser UCLA 1 CSC Trigger Primitives Test Beam Studies Main Test Beam 2003 Goals: Verify the peripheral crate.

Endcap Muon meeting: CMU, Oct 19, 2003 J. Hauser UCLA 1 CSC Trigger Primitives Test Beam Studies Main Test Beam 2003 Goals: Verify the peripheral crate.
Using the Trigger Test Stand at CDF for Benchmarking CPU (and eventually GPU) Performance Wesley Ketchum (University of Chicago) 10.27.2010.

Using the Trigger Test Stand at CDF for Benchmarking CPU (and eventually GPU) Performance Wesley Ketchum (University of Chicago)
GEM Design Plans Jason Gilmore TAMU Workshop 1 Oct 2013 1.

GEM Design Plans Jason Gilmore TAMU Workshop 1 Oct
US CMS Phase 2 R&D Discussion 30-July-2013 “Phase 2 muon R&D” J. Hauser, UCLA  Add redundancy (power) to trigger where most needed  First and innermost.

US CMS Phase 2 R&D Discussion 30-July-2013 “Phase 2 muon R&D” J. Hauser, UCLA  Add redundancy (power) to trigger where most needed  First and innermost.
Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control.

Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control.
CHEP March, 2003. B. Scurlock, University of Florida1 D. Acosta, V. Golovtsov, M. Kan, A. Madorsky, B. Scurlock, H. Stoeck, L. Uvarov, S.M. Wang University.

CHEP March, B. Scurlock, University of Florida1 D. Acosta, V. Golovtsov, M. Kan, A. Madorsky, B. Scurlock, H. Stoeck, L. Uvarov, S.M. Wang University.
The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System D.Acosta, A.Madorsky, B.Scurlock, S.M.Wang University of Florida A.Atamanchuk,

The Track-Finding Processor for the Level-1 Trigger of the CMS Endcap Muon System D.Acosta, A.Madorsky, B.Scurlock, S.M.Wang University of Florida A.Atamanchuk,
Global Trigger H. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, J. Strauss,

Global Trigger H. Bergauer, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H. Sakulin, J. Strauss,
Bologna, 10/04/2003 Workshop on LHC Physics with High P t Muon in CMS R.Travaglini – INFN Bologna Status of Trigger Server electronics Trigger boards TB.

Bologna, 10/04/2003 Workshop on LHC Physics with High P t Muon in CMS R.Travaglini – INFN Bologna Status of Trigger Server electronics Trigger boards TB.
An Asynchronous Level-1 Tracking Trigger for Future LHC Detector Upgrades A. Madorsky, D. Acosta University of Florida/Physics, POB 118440, Gainesville,

An Asynchronous Level-1 Tracking Trigger for Future LHC Detector Upgrades A. Madorsky, D. Acosta University of Florida/Physics, POB , Gainesville,
Printed by www.postersession.com Topical Workshop on Electronics for Particle Physics TWEPP-08, Naxos, Greece / 15-19 September 2008 MEZZANINE CARDS FOR.

Printed by Topical Workshop on Electronics for Particle Physics TWEPP-08, Naxos, Greece / September 2008 MEZZANINE CARDS FOR.
Saverio Minutoli INFN Genova 1 1 T1 Electronic status Electronics Cards involved: Anode Front End Card Cathode Front End Card Read-Out Control card VFAT.

Saverio Minutoli INFN Genova 1 1 T1 Electronic status Electronics Cards involved: Anode Front End Card Cathode Front End Card Read-Out Control card VFAT.
13 March 2007G. Rakness (UCLA) 1 Minus side slice test status Greg Rakness University of California, Los Angeles UCLA phone meeting 13 March 2007.

13 March 2007G. Rakness (UCLA) 1 Minus side slice test status Greg Rakness University of California, Los Angeles UCLA phone meeting 13 March 2007.
RPC PAC Trigger system installation and commissioning How we make it working… On-line software Resistive Plate Chambers Link Boxes Optical Links Synchronization.

RPC PAC Trigger system installation and commissioning How we make it working… On-line software Resistive Plate Chambers Link Boxes Optical Links Synchronization.
Status of the CSC Track-Finder Darin Acosta University of Florida.

Status of the CSC Track-Finder Darin Acosta University of Florida.
M. Lo Vetere 1,2, S. Minutoli 1, E. Robutti 1 1 I.N.F.N Genova, via Dodecaneso, 33 - 16146 GENOVA (Italy); 2 University of GENOVA (Italy) The TOTEM T1.

M. Lo Vetere 1,2, S. Minutoli 1, E. Robutti 1 1 I.N.F.N Genova, via Dodecaneso, GENOVA (Italy); 2 University of GENOVA (Italy) The TOTEM T1.
Technical Part Laura Sartori. - System Overview - Hardware Configuration : description of the main tasks - L2 Decision CPU: algorithm timing analysis.

Technical Part Laura Sartori. - System Overview - Hardware Configuration : description of the main tasks - L2 Decision CPU: algorithm timing analysis.
Simulation of GEM-CSC Integrated Trigger: Status and Plans US CMS EMU Workshop 2013-10-01 Vadim Khotilovich, Texas A&M University for GEM DPG group.

Simulation of GEM-CSC Integrated Trigger: Status and Plans US CMS EMU Workshop Vadim Khotilovich, Texas A&M University for GEM DPG group.

Similar presentations

Ads by Google