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Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 1 Power Estimation FlexSoc Seminar Series – 2004-03-15 Daniel Eckerbert

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Presentation on theme: "Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 1 Power Estimation FlexSoc Seminar Series – 2004-03-15 Daniel Eckerbert"— Presentation transcript:

1 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 1 Power Estimation FlexSoc Seminar Series – 2004-03-15 Daniel Eckerbert daniel.eckerbert@ieee.org

2 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 2 Outline Why power estimation? Power macromodeling Future directions for power estimation Most pictures (non-Matlab-plots) are courtesy of Intel Corp.

3 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 3 Why Power Estimation? (Conference-Presentation Answer) Heat removal is expensive (fans, heat-sinks) Energy stored in battery is limited Power delivery is expensive (area, reliability, verification, packaging)

4 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 4 Why Power Estimation? (FlexSoC Answer) Compiler optimizations “Designing” range of chips for certain applications ??? You tell me!

5 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 5 Power Reduction Techniques Activity reduction Supply voltage scaling Leakage reduction (cut-off techniques, stacking etc) But, by how much does the power of a specific design needs to be reduced? And which power mechnism constitutes a problem?

6 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 6 Power Dissipation Basics

7 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 7 From Where Does the Power Increase Stem?

8 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 8 Increased Integration

9 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 9 Increased Integration 120 billion transistors per wafer!!! SRAM chips fabricated on a 300mm wafer

10 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 10 Increased Density

11 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 11 Power Density

12 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 12 Heat Removal (die)

13 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 13 Heat Removal (package)

14 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 14 Power Macro Modeling

15 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 15 Architecture Level Power Macromodeling à la Wattch P=0.1*P sw (α max )+P sw (α,state)

16 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 16 What Do We Want from a Power Estimation Methodology? Accurate Fast Provide information for power reduction

17 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 17 Levels of Power Estimation

18 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 18 Why Use Macro Models? Circuit simulations excessively time- and memory-consuming Designers need to run long traces to compare solutions (only possible using macro models)

19 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 19 Estimation Tool Run-Times Run-timeHSpice * PowerMill * Macro ** 16b Han- Carlson 12d14h8h49m (30x) 6m43s (2700x / 80x) 8b Multiplier29d6h17h37m (40x) 9m42s (4300x / 100x) 32b MultiplierN/A14d10h2h2m (N/A / 170x) * Highly optimized code by team of software designers ** Highly unoptimized C++ code by one overworked circuit designer

20 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 20 Precision Circuit simulations give full or close to full precision (depending on extraction) Macro modeling can give range of precision levels (with a maximum precision determined by methodology) Macro model precision is limited by the characterization

21 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 21 Power Estimation Flow Characterization –Requires lower level simulations –Has to support maximum precision –One-time only, can afford to be slow Estimation –Macro-model only –Can support multiple levels of precision –Frequently run, has to be fast

22 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 22 Characterization

23 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 23 Estimation

24 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 24 Switching Power (Circuit Level)

25 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 25 Switching Power (Early Power Macro Models)

26 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 26 Switching Power (VLSI Research Group Style) Equation-based 0→1 tracking, even for intermediate nodes depending on accuracy Physical model based on nodal capacitances and voltage swings Enables semi-automatic characterization

27 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 27 Short-Circuit Power (Circuit Level)

28 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 28 Short-Circuit Power (Macro Model)

29 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 29 Interconnect Modeling

30 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 30 CRC

31 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 31 RLC

32 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 32 Subthreshold-Leakage Power

33 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 33 Subthreshold-Leakage Power (Circuit Level)

34 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 34 Subthreshold-Leakage Power Stacking effects Long settling times …?

35 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 35 Subthreshold-Leakage Power (Macro Model) Equation-based model considering on- and off-states of the transistors constituting the gate Enables semi-automatic characterization Possible extensions for stacking Possible extensions for multiple clock-cycle settling times

36 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 36 Gate-Leakage Power

37 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 37 Oxide Thickness 12 Å

38 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 38 Oxide Thickness

39 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 39 Gate-Leakage Power (Circuit Level) Enough equations and theory to use up the entire FlexSoC seminar series

40 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 40 Gate-Leakage Power (Macro Model) Equation-based model considering on- and off-states of the transistors constituting the gate Enables semi-automatic characterization Complications include leakage paths originating in one gate and ending up in another gate

41 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 41 Separating Power Dissipation Mechanisms

42 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 42 Leakage Power Increase

43 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 43 Active vs. Leakage Power

44 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 44 Separation of Mechanisms (Rise- and Fall-Times)

45 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 45 Separation of Mechanisms (Supply-Voltage Scaling)

46 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 46 Mismatch for Methodologies without a Leakage Component

47 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 47 Mismatch for Methodologies without Leakage or Dynamica Frequency and Supply Scaling

48 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 48 Added Complications

49 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 49 Complex Gates Most circuit-level models are only valid for a single transistor or an inverter Macromodels have to be able to account for large components, 32b multipliers etc Complexity increases super-linearly with the number of transistors in the component

50 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 50 Non-Conforming Components There are classes of components which do not conform to the presented basic models: Clock generators Memories etc

51 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 51 Clock Generation (DLL)

52 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 52 Clock Generators (Delay Element)

53 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 53 Non-Linear Frequency Dependence for Certain Types of Components

54 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 54 Dynamic Precision Different architectures might impose different precision requirements for different components (static during estimation) Different operating modes might warrant different need for precision (changes during estimation)

55 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 55 Conclusions Power estimation is not simply about averaging the current through the supplies Circuit simulation is too slow A lot of research is needed to enable high- level power estimation for future designs: some in mechanism modeling but more importantly in the estimation framework

56 Chalmers University of Technology FlexSoC Seminar Series – 2004-03-15Page 56 Power estimation is not as easy as it looks

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