1. EE 348: Lecture #03 EE 348: Lecture #03 Circuit Level Models Of CMOS Technology Transistors Prof. John Choma, Jr. University of Southern California Department of Electrical Engineering-Electrophysics University Park: MC: 0271 Los Angeles, California 90089-0271 213-740-4692 (USC  ) 626-915-0944 (FAX  ) 818-384-1552 (CELL  ) johnc@almaak.usc.edu Jchoma1106@aol.com Spring 2003 Semester

2. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 66 Lecture Overview Static MOS Model  Cutoff Region  Ohmic (Triode) Region  Saturation Region  Subthreshold Region Short Channel Effects In Saturation  Channel Length Modulation  Substrate (Bulk) Phenomena  Mobility Degradation  Carrier Velocity Saturation Small Signal Model In Saturation  Low Frequency Equivalent Circuit  High Frequency Equivalent Circuit Example: Inverter Analysis

3. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 67 N—Channel MOSFET For Low Signal Frequencies

4. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 68 P—Channel MOSFET For Low Signal Frequencies

5. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 69 Static Cutoff Model Cutoff Regime Is V gs < V hn For N-Channel  V hn Is Threshold Voltage, Which Is Functionally Dependent On Bulk-Source Voltage, V bs  Model Is Simply I d = 0 (Open Circuited Drain) Cutoff Regime Is V sg < V hn For P-Channel  V hn Is Threshold Voltage, Which Is Functionally Dependent On Source-Bulk Voltage, V sb  Model Is Simply I d = 0 (Open Circuited Drain) Cutoff Operation  Commonly Encountered In Digital Applications  Rarely Encountered In Analog Configurations

6. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 70 Static Triode Model Triode Regime Is V gs  V hn & V ds < V gs – V hn Parameters  K n Is Transconductance Coefficient (Hundreds Of  mhos/volt)  ε ox Is Silicon Dioxide Dielectric Constant (345 fF/cm)  μ n Is Electron Mobility Of Source -To- Drain Electrons  Typically In Mid-Hundreds Of cm 2 /volt-sec  Temperature Dependent  Inverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. T o Is Arbitrary Reference Absolute Temperature

7. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 71 Triode Model For P—Channel Triode Regime Is V sg  V hn & V sd < V sg – V hn Parameters  K p Is Transconductance Coefficient (Hundreds Of  mhos/volt)  ε ox Is Silicon Dioxide Dielectric Constant (345 fF/cm)  μ p Is Electron Mobility Of Source –To- Drain Electrons  Typically In Low-Hundreds Of cm 2 /volt-sec  Temperature Dependent  Inverse Temperature Dependence Of Mobility Makes MOS A Negative Temperature Coefficient Transistor. T o Is Arbitrary Reference Absolute Temperature

8. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 72 Triode Regime Characteristics Triode Regime  Also Known As Ohmic Regime Or Ohmic Region  Often Used As Active Two Terminal Resistance  Note V ds = V gs – V gd V hn ; That Is, Both The Gate-Source AND The Gate-Drain Biases Must Exceed Threshold Drain-Source Resistance  Small Signal Conductance  For V ds << (V gs – V hn )  For Small Drain-Source Voltages, Transistor Behaves As A Linear Resistance In Its Ohmic Regime

9. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 73 Saturation Regime Model Saturation Requires V gs  V hn & V ds  V gs – V hn  Parameters  Drain Saturation Voltage, V dss  Drain Saturation Current, I dss  I-V Characteristic Comments On Saturation Regime  Saturation Regime Is The Region Where Transistors Are Commonly Biased For Linear Signal Processing Applications  Current Is Constant, Independent Of Drain-Source Voltage For All V ds  V dss  Transistor Behaves As A Current Source At Its Drain-Source Port  Current Is Actually Voltage Controlled Current Source  Controlled By Gate-Source Voltage, V gs  Control Is Nominally Square Law Relationship

10. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 74 Linearity In Saturation Differential Amplifier Differential Response

11. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 75 Comments: Differential Amplifier Fundamental Results  Output Voltage  Gain Linearity  Output Voltage Is Proportional To Differential Input Voltage  Gain Is Independent Of Differential Input Voltage  Gain Is Controllable By Common Mode Input Voltage  Note That No Small Signal Modeling Approximation Is Invoked

12. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 76 Subthreshold Regime Model Subthreshold Requires 0 < V gs < V hn – 2nV T & V ds  2nV T  V T = kT/q = 26 mV @ 27 °C  Factor n Is Empirical And Satisfies 1.1 < n < 2.0  Drain Current: Comments  Gate-Source Voltage Is Barely Above Threshold Level, While Drain-Source Voltage Is Restricted To Nominally Less Than 100 mV  Operation In Subthreshold Is Useful Only For Low Frequency, Low Power Analog Signal Processing Applications  Static Volt-Ampere Characteristic Emulates That Of Bipolar Transistor Action

13. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 77 Review: Simple MOSFET Model Low Signal Frequencies Comments  Above Relationships Written For N-Channel; Analogous Expressions For P-Channel  Known As “Schichman-Hodges” Model Or “Long Channel Model Approximation”  Valid Only For Low Signal Frequencies

14. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 78 Sample MOSFET Static Curves K n (W/L) = 100 mmho/volt V hn = 900 mvolt Nominally Linear Resistance

15. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 79 MOSFET In Cutoff Voltages  V ds  0  V bs  0 Gate-Source  V gs = V ox + V y  V ox Is Voltage Across Oxide  V y Is Voltage Between Oxide- Semiconductor Interface And Source Ionic Charges In Channel Are Immobile

16. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 80 Comments: Cutoff Regime Channel  Depleted Of Free Carriers  No Current Conduction Path Between Source And Drain  Only Current Is Leakage  Holes From Drain & Source  Electrons From Bulk Depletion Regions  At Source-Bulk And At Drain-Bulk Because V bs  0  Wider In Drain Region Because V ds > 0

17. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 81 Channel Inversion In Ohmic Regime Gate Voltage Inversion  Weak: n = N i @ V = V F  Strong: n = N A @ V y = 2V F  V F : Fermi Potential N i Is Intrinsic Carrier Concentration Of Silicon (about 10 10 atoms/cm 3 at 27 °C) n Is Concentration Of Free Electrons In Channel

18. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 82 Channel Inversion: Ohmic, V ds > 0 Channel  Narrows At Drain  V gd = V gs – V ds Decreases  Resistance Becomes Dependent On V ds  Resistance Is Resultantly Nonlinear Current  Electrons Transported From Source –To- Drain Principally In Channel Via Conventional Diffusion Mechanisms  But Some Electrons Are Transported By Drift Through Depletion Region Between Drain Site And Electron Channel “Wedge”

19. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 83 Comments: Ohmic Regime Uniform Channel Resistance  Behaves As Implanted Resistor  Contacts Are Source & Drain  Conductance With Drain-Source Bias  Behaves As Tapered Resistor  Contacts Are Source & Drain  Conductance

20. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 84 Channel Inversion: Pinchoff At Pinchoff  V gd = V hn  V ds = V gs – V hn = V dss  Gate-Drain Voltage Barely Supports Strong Inversion  Channel Thickness Narrows To Zero At Drain Site Resistance  Dynamic Conductance (Slope Of I d vs. V ds Curve) Is Zero  Electron Transport Mechanism From Source -To- Drain Now Shifts From Diffusion To Drift

21. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 85 Channel In Saturation Regime Channel  Channel Thickness Reduces To Zero When Voltage Across Channel Is V dss  For V ds > V dss V dss Must Be Dropped With Respect To Source Within Channel  Voltage (V ds – V dss ) Dropped Across Depletion Zone Between Channel And Drain Phenomenon Is Channel Length Modulation

22. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 86 Channel Length Modulation Modified I/V Characteristic In Saturation  I dss Is Current Flowing When Channel Is Of Length L  Modified Current Is Effectively I dss Corrected For A Channel Length Of (L –  L) Channel Length Modulation Voltage  Substrate-Drain/Source Junction Potential:  Intrinsic Carrier Concentration: (N i In cm -3 When T In °K)

23. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 87 Channel Length Parameters Channel Length Modulation Voltage  Ideally, V λ    Infinitely Large V Implies MOSFET Behaves As An Ideal Current Source (Independent Of V ds ) Controlled By V gs  Progressively Shorter Channels Diminish V λ  Large Substrate Doping Concentration Encourages Large V λ Intrinsic Carrier Concentration  Empirical Relationship Nominally Valid Only For Silicon  N i = 10 10 cm -3 At Temperature T = 27 °C = 300.2 °K  N i Nominally Doubles For Each 11 °C Rise In Silicon Temperature Miscellaneous Parameters   s Is Silicon Dielectric Constant (1.05 pF/cm)  q Is Magnitude Of Electron Charge (1.6 x 10 -19 Coulomb)

24. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 88 Threshold Voltage Modulation Modified Saturation Region Drain Current Bulk Voltage-Dependent Threshold Voltage  Threshold Voltage Increases With Substrate-Source Reverse Bias  Ideally, Threshold Voltage Is Constant, Independent Of V bs  Constant Threshold Voltage Requires Thin Oxide And/Or Low Substrate Dopant Level

25. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 89 Threshold Voltage Characteristic N A = 5 x 10 14 cm -3 ; T = 27 °C

26. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 90 Mobility Degradation Electric Field Problems  Short Channels And/Or Thin Oxides Conduce Large Lateral And Vertical Channel Fields For Even Moderate Drain-Source Voltages  Large Fields Impart Increasing Energy To Free Channel Charges, Thereby Causing More Carrier Collisions And A Mobility That Degrades From A Value Of μ n –to- A Value, Say μ ne  At Low Fields, Carrier Velocity Is Proportional To Lateral Fields  At Large Lateral Fields, The Carrier Velocity, v, Saturates To A Value, v sat, Which In Silicon Is Around 0.1  m/pSec  Saturation Occurs When Lateral Field, E h, Exceeds A Critical Value, E c, Which In Silicon Is About 5 volts/  m Mobility And Field

27. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 91 Carrier Velocity And Mobility

28. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 92 Alternative Mobility Relationships Critical Voltage Parameter Comments  Crude Approximation For Lateral Field, E h  Channel Length In Field Expression Should Be (L –  L), But Channel Modulation Is Accounted For By Channel Modulation Voltage, V  Critical Voltage For L = 0.25 μm Is V c = 1.25 volts Transconductance Density:

29. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 93 Volt-Ampere Impact Of Mobility Static Drain Current In Saturation High Fields  V gs - V hnc >> V c  V c = LE c  v sat = μ n E c Comments  Drain Current Now Scales With W, As Opposed To (W/L)  Drain Current Almost Linear W/R To Gate-Source Voltage

30. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 94 Comments: Velocity Saturation Most Of The Channel Is Depleted  Common For Deep Submicron Geometries (L < 0.2  m)  Free Electrons Concentrated Near Source Characteristics  Drain Current Nominally Linear With Gate-Source Voltage  Limited Overdrive (V ds – V dss ) Capability  Effective Transconductance Is Low (Generally Of Order Of Low Tens of Millimhos For Routine Geometries)

31. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 95 MOS Large Signal Model C gd  Gate-Drain Capacitance C gs  Gate-Source Capacitance C db  Drain-Bulk Capacitance C sb  Source-Bulk Capacitance C old  Drain Overlap Capacitance C ols  Source Overlap Capacitance r g  Gate-Source Resistance r dd  Drain Ohmic Resistance r ss  Source Ohmic Resistance r bb  Bulk Ohmic Resistance r db  Bulk/Drain Ohmic Resistance r sb  Bulk/Source Ohmic Resistance DBD  Bulk-Drain Diode DBS  Bulk-Source Diode

32. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 96 MOS Capacitances In Saturation A d  Drain-Bulk Junction Area A s  Drain-Source Junction Area C jo  Zero Bias Density Of Junction Depletion Capacitance C db, C sb  High Tens of fF C gs  Tens of fF C gd, C old, C ols  Few fF (Representative Submicron Device)

33. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 97 Comments On Model Overlap Capacitances  Generally Negligible In Self-Aligning Processes  Possible Exception Is C gd For Deep Submicron  Proportional To Device Depth, W  W Necessarily Large For Reasonable Transconductance Diodes Are Routinely Non-Conductive Resistances  r dd, r ss, r bb, r sb, r db Normally Have Negligible Electrical Effects  r g Is Gate-Source Resistance  Allows Accurate Modeling Of Transconductance Phase Response  Negligible Effect For Frequencies Well Below Unity Gain Frequency  Semi-Empirical Expression

34. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 98 First Order Small Signal Model Transconductances Channel Resistance

35. University of Southern California/Choma EE 348, Spring 2003: Lecture #03 99 Comments: First Order Model Model Is For “Long Channels” Where Square Law I-V Characteristic Is Valid All Ohmic Resistances Are Generally Ignored Gate Resistance Ignored Because Of Presumption Of Signal Frequencies Much Smaller Than Unity Gain Device Frequency

36. University of Southern California/Choma EE 348, Spring 2003: Lecture #03100 Short Channel Small Signal Effects Static (Low Frequency) Drain Current Intermediate Parameters: Resistance: Transconductances:

37. University of Southern California/Choma EE 348, Spring 2003: Lecture #03101 Hypothetical Transistor Physical Parameters N A = 5.5(10) 14 cm -3 N D = 5(10) 21 cm -3 N i (T o ) = (10) 10 cm -3  s = 1.05 pF/cm  ox = 345 fF/cm  n = 420 cm 2 /volt-sec E c = 5 volts/  m Comments  Internal Temperature, T, Is Always Larger Than Ambient Reference Temperature, T o  Compare Long And Short Channel Characteristics Device Parameters T ox = 18 Å (Angstroms) L = 0.18  m V hn = 650 mV T = 50 °C = 323.2 °K T o = 27 °C = 273.2 °K W = 1.8  m Circuit Operation V ds = 1.8 volts V gs = 0.95 volts V bs = -1 volts  Saturation Region Bias  Bulk Is Back Biased

38. University of Southern California/Choma EE 348, Spring 2003: Lecture #03102 Transistor Characteristics Peripheral Calculations   V F = 263.8 mV  (Fermi Potential)   V j = 974.3 mV  (Substrate-Drain/Source Junction Potential)   V  = 25.15  V  (Threshold Body Effect Voltage)   V = 366.8 mV  (Channel Length Modulation Voltage)   V c = 900 mV  (Mobility Degradation Voltage)   V dss = 296.3 mV  (Drain Saturation Voltage)   V hnc = 653.7 mV  (Compensated Threshold Voltage)   K n = 721  mho/V  (Transconductance Parameter)   C ox = 1.92  F/cm 2  (Oxide Capacitance Density) Device Performance   I dss = 316.25  A  (Long Channel Static Drain Current)   I dQ = 1.213 mA  (Actual Static Drain Current)   g mf = 2.135 mmho  (Long Channel Forward Transconductance)   g mfs = 6.527 mmho  (Actual Forward Transconductance)   b = 0.00292  (Bulk Transconductivity Factor)   g mb = 19.079  mho  (Substrate/Bulk Transconductance)   r o = 1.54 K   (Drain-Source Channel Resistance)

39. University of Southern California/Choma EE 348, Spring 2003: Lecture #03103 Device Unity Gain Frequency Short Circuit Current Gain: Unity Gain Frequency: Comments   T << g mf /(C gd +C old )  Shichman-Hodges Model For g mf

40. University of Southern California/Choma EE 348, Spring 2003: Lecture #03104 High Frequency Observations Long Channel Approximation:  Inversely Proportional To Nominally The Square Of Channel Length  Degradation Incurred By Gate Overlaps  Decreases With Temperature Because Of Mobility Dependence Short Channel Approximation:  Assume Small Overdrive And Large f c  Total Capacitance, C T, Is Net (C gd + C gs )  Unity Gain Frequency Is g mfs /C T  Note Nominal Inverse Proportion To L, Not L 2 Actual Unity Gain Frequency  Smaller Of Long And Short Channel Results  For Preceding Example With L d /L = 0.1  f Tl = 63.13 GHz  f Ts = 51.01 GHz f T = 51 GHz

41. University of Southern California/Choma EE 348, Spring 2003: Lecture #03105 Small Signal Models Traditional Model  Assumes Saturation Regime  C gs And C gd Include Overlap Alternate Model  Current Control  Assumes Saturation  Gate Capacitances Include Overlap Effects  Useful When Source Degeneration Is Used

42. University of Southern California/Choma EE 348, Spring 2003: Lecture #03106 Common Source Inverter PROBLEM: Determine The Low Frequency, Small-Signal Voltage Gain, A v (0) = V os /V s, And, Assuming C L Is The Dominant Circuit Capacitance, Find The 3-dB Bandwidth And The Unity Gain Frequency Of The Amplifier.

43. University of Southern California/Choma EE 348, Spring 2003: Lecture #03107 Effective Load Resistance Model Parameters Account For Short Channels Analysis With All Internal Ohmic Resistances Ignored: Resistance Is Roughly Inverse Forward Transconductance

44. University of Southern California/Choma EE 348, Spring 2003: Lecture #03108 Low Frequency Voltage Gain Gain Long Channel Approximation

45. University of Southern California/Choma EE 348, Spring 2003: Lecture #03109 High Frequency Considerations Substantial Capacitive Loading At Output Port Due To Substrate Negligible C f In Self-Aligning Gate Technology Model Ignores Bulk Transconductance Because Source And Bulk Of Driver Are Shorted To Ground All Gate-Source And Gate-Drain Capacitances Include Overlap Effects Gate-Drain And Drain-Bulk Load Capacitances And Source-Bulk Driver Capacitances Are AC Short Circuited

46. University of Southern California/Choma EE 348, Spring 2003: Lecture #03110 High Frequency Gain & Bandwidth Dominant Pole  Likely p 1  R s Is Typically Small (50 Ohms Or Less) In High Frequency Circuits  Large Capacitive Loading At Output Port  Bandwidth, B, (In Radians/Sec) Is Resultantly Roughly p 1 Gain-Bandwidth Product:

47. University of Southern California/Choma EE 348, Spring 2003: Lecture #03111 Dominant Pole Response For p 2 >> P 1 : Unity Gain Frequency  Frequency At Which Gain Magnitude Degrades To One (0 dB)  True Dominant Pole Response Has p 2 >  u  Advantage Of This Requirement Is Principally Stability In Feedback Networks  Promotes Adequate Phase And Gain Margins (Discussed Later)  Feedback, Although Not Necessarily Purposefully Imposed, Is Unavoidable In High Frequency Networks

48. University of Southern California/Choma EE 348, Spring 2003: Lecture #03112 Frequency Response Zero Frequency Gain = 6 = 15.6 dB

49. University of Southern California/Choma EE 348, Spring 2003: Lecture #03113 Phase Response