1. הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה
הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה
1:09:38 AM
Modeling and Optimization of VLSI Interconnect Lecture 6: Interconnect power
Avinoam Kolodny
Konstantin Moiseev
VLSI-מודלים ואופטימיזציה של קווי חיבור ב

2. הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה
הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה
1:09:38 AM
Outline
Interconnect power modeling
Definition
Activity factor (AF) and signal probability (SP) and relations between them
Cross-coupling power. Miller Coupling Factor for timing and power
Relation between MCF and AF
AF and SP generation
Interconnect power breakdown
Interconnect length distribution
Local and global interconnects and their power
Clock power
Interconnect power of total power
Interconnect power prediction
Interconnect length prediction
Rent’s rule
Donath’s model
Fanout prediction
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3. 1 Google search = ? Same energy as 11-watt light bulb for an 1 hr
Emit 7gr CO2
There are 0.4B Google searches daily
Adopted from Muhammad Abozaed, Intel

4. So why power is important?
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1:09:38 AM
So why power is important?
Mobile – battery life
Reliability - Power density
User experience – skin temperature
Servers – cooling costs, environmental heating
Some well-known pictures
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5. Electrical Energy Energy is defined as the ability to do work
Electrical energy is energy stored in an electric field or transported by an electric current
Electrical energy can be:
Dissipated as heat by an electric current flowing through resistor
Stored in a capacitor
Transformed to magnetic field energy
The work performed by current on section with voltage difference during time is:

6. Power Power is work performed per unit time
Measured in Watts
In VLSI, the power is usually either consumed or dissipated
Consumed from the source
Dissipated by resistors (converted to heat)
The average power dissipation by current with voltage difference during time is:

7. Power dissipation sources
Dynamic power
Static power
Short-circuit power

8. Energy dissipation in RC circuit
First stage – charging capacitor: R
Capacitor current:
Energy stored in the capacitor:
Energy dissipated by the source:
Energy dissipated by the resistor (converted to heat): I VR C
VDD Vc
Assumption:

9. Energy dissipation in RC circuit
Second stage – discharging capacitor: I R
Capacitor current:
Energy freed by the capacitor:
Energy dissipated by the source:
Energy dissipated by the resistor (converted to heat): VR C
VDD Vc
Assumption:

10. Dynamic power dissipation in VLSI
So, for two capacitor switches (charge and discharge), the energy dissipated is CVDD2
For two switches of signal during time T (clock period), the average power dissipation is
If the signal switches times in average during time T, then the average power dissipation is
is called activity factor

11. Dynamic power contributors
Dynamic power dissipation:
The capacitance is contributed by three elements:
Self-capacitance and cross-coupling capacitance
Area and fringe capacitance
Coupling capacitance

12. Coupling capacitance calculation
Coupling capacitance value depends on neighbor wires
For quiet neighbors (tied to VDD or ground)
For switching neighbors the capacitance will depend on switching direction
Power calculation by equivalent circuit method
Power calculation by application of Miller’s theorem

13. Equivalent circuit method
Equivalent circuit for two coupled lines:
Simplest case – wire is switched from 0 to VDD; neighbor is quite and tied to ground, R1=R2
Energy dissipated by each resistor (wire) in this case is
Total energy dissipated is

14. Equivalent circuit method
For all cases of one quite wire and one switched wire the same results as in previous slide are obtained
Second case – both wires are switched simultaneously from 0 to VDD
The current through resistors is
( is voltage on the capacitor)
No power dissipation in this case!
Before
After

15. Equivalent circuit method
Third case – both wires are switched simultaneously in opposite directions
Current in the circuit:
Energy consumed by the second source is zero (voltage of source is zero)
Energy consumed by the first source:
No energy change of the capacitor
It means all the energy is dissipated by resistors
Each resistor dissipates , totally
( is the capacitor voltage)
Before
After

16. Miller’s theorem
Z is impedance

17. Usage of Miller’s theorem for coupling capacitance and power calculations
disconnected

18. Observations
Miller’s theorem gives the same results for total power dissipation as equivalent circuit method, however, the results for each wire power dissipation are inaccurate
Total power dissipation calculated by using of both methods is follows:
For one-wire switch – power dissipation is
For simultaneous switch in the same direction – there is no power dissipation
For simultaneous switch in opposite directions:

19. Miller factor for power
Miller factor is used in order to account effects of changing coupling capacitance due to switching
Nominal coupling capacitance is multiplied by Miller Coupling Factor (MCF) in order to obtain real capacitance:
For one-wire switching, MCF = 1
For switching in the same direction, MCF = 0
For switching in opposite directions, MCF = 4

20. Recall: MCF for delay

21. Activity factor
Activity Factor (AF) ( a.k.a toggle rate) is an average fraction of cycles in which signal changes from 0 to 1 or from 1 to 0, as compared to clock signal
Clock toggles twice a cycle, so its AF = 1
Combinational logic data signal normally will have maximum AF = 0.5
Domino signal can have AF = 1
Is it possible for signal to have AF > 1?
Yes, because of glitches
clk
data
out
Domino d1
out
clk d2

22. Signal probability
Signal probability (SP) is an average fraction of cycles in which signal has logic value of “1”
SP = 0.5
SP = 1
SP ≈ 1

23. Relation between MCF and AF
Assume two neighbor uncorrelated signals make and
transitions during clock cycles
It can be shown that number of simultaneous transitions of the signals is negligible no more than 4
Therefore, energy dissipated by cross capacitance between signals is
The power dissipated during cycles is:
For the same reason, it is usually assumed that MCF=1 for uncorrelated signals

24. Activity Factors Generation
Power test vectors generation
(worst case for high power, unit stressing)
RTL full-chip simulation
(results in blocks primary inputs: Activity,Probability)
Monte-Carlo based block inputs generation
(based on the RTL statistics)
Transistor level simulation - per block
(Unit delay, tuning for glitches)
Per node activity factor
Source -”Intel® Pentium® M Processor Power Estimation, Budgeting, Optimization, and Validation”, ITJ 2003

25. Interconnect power breakdown case study

26. Case study Low-power, state-of-the-art μ-processor
Dynamic switching power analysis
Interconnect attributes:
Length
Capacitance
Fan Out (FO)
Hierarchy data
Net type
Activity factors (AF)
Miscellaneous.

27. Power Estimation accuracy
Simulated activity density
IREM measurement
Source -”Intel® Pentium® M Processor Power Estimation, Budgeting, Optimization, and Validation”, ITJ 2003

28. Interconnect Length Distribution
Source: Shekhar Y. Borkar, CRL - Intel

29. Interconnect Length Distribution
Nets vs. Net Length
Log – Log scale
Exponential decrease with length
Global clock – not included

30. Total Dynamic Power Peak 2 Peak 1 Total Dynamic Power
Total Power vs. Net Length
Peak 1
Nets: 390k
Cap: 10[nF]
FO: 2
AF:
Peak 2
Nets: 75k
Cap: 20[nF]
FO: 20
AF: 0.055
Total Dynamic Power
Global clock – not included
Local nets = 66%
Global nets = 34%

31. Local and Global Interconnect
Local Power breakdown vs. Net Length
Local and Global IC are different:
Number by Length breakdown
IC breakdown – cap and power
Fan out
Metal usage
AF is similar
Global Power breakdown vs. Net Length

32. Power Breakdown by Net Types
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Power Breakdown by Net Types
Global clock included
Interconnect power
(Interconnect only)
Total power
(Gate, Diffusion and Interconnect)
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33. Interconnect Length Prediction
Technology projections - ITRS
Interconnect length predictions:
ITRS model: 1/3 of the routing space
Davis model:
Rent’s rule based
Predicts number of nets as function of: the number of gates and complexity factors
Models calibrated based on the case study ?
Time

34. Future of Interconnect Power
Dynamic Power breakdown
Gate
Diffusion
Interconnect
Source - ITRS 2001 Edition adapted data
Technology generation [μm]
Interconnect power grows to 65%-80% within 5 years !
(using optimistic interconnect scaling)

35. Interconnect Power Prediction
הטכניון - מ.ט.ל. הפקולטה להנדסת חשמל - אביב תשס"ה
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Interconnect Power Prediction
Number of Nets (normalized)
Interconnect length projection
100
The number of nets vs. unit length – Modified Davis model
The dynamic power average breakdown 10 1
0.1
Upper local bound
0.01
Lower global bound
0.001
Dynamic power breakdown
Interconnect
Power
Diffusion
Gate
Local
Intermediate
Global
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36. Interconnect Power Model
Multiplication of the number of interconnects with power breakdowns gives:
Projected dynamic power vs. net length
Power (normalized)
Length [μm]
The power model matches processor power distribution !

37. Experiment - Power-Aware Router
Routing Experiment optimizing processor’s blocks
Local nodes (clock and signals) consume 66% of dynamic power
10% of nets consume 90% of power
Min. spanning trees can save over 20% Interconnect power
Routing with spacing can save up to 40% Interconnect power
Small block’s local clock network

38. Power-Aware Router Flow
Clock tree: high FO, long lines, very active
Avoiding congestion
Rip-up: not high power nets
Followed by downsizing

39. Results - Power Saving Average saving results: 14.3% for ASIC blocks 1
Downsize saving
Average
Router saving
Average saving results: 14.3% for ASIC blocks 1
1 - Estimated based on clock interconnect power

40. Backup

41. Rent’s Rule Empirical rule Terminals versus Number of gates.
Taken from Krishna Saraswat in SLIP 2000
Empirical rule
Terminals versus
Number of gates.
Published by:
B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs.
IEEE Trans. on Comput., vol. C--20: pages , 1971.
The graph comes from Intel – from 1971 (4004) to 1996 (pentium pro).

42. Rent’s parameters Rent’s rule: T = k N r T = # of I/O terminals (pins)
N = # of gates
k = avg. I/O’s per gate
r = Rent’s exponent
can be: 0 < r < 1 , but common -
(simple) 0.5 < r < 0.75 (complex)
N gates
T terminals
r is below 1 – otherwise – we would have more terminals as we go up in the hierarchy.

43. Rent’s Rule Example Lets assume Rent’s parameters: r=0.79 and k=2.
For a single gate: N=1
For a block of four gates: N=4
Fan out is implied by Rent.

44. Is Rent’s rule a coincidence ?
Random circuits do not obey Rent.
Rent’s parameters are correlated with Place and Route algorithms.
P. Verplaetse J. Dambre D. Stroobandt J. Van Campenhout. On Partitioning vs. Placement Rent Properties. In Proc. of Intl. Workshop on System-Level Interconnect Prediction, March 2001.
Self similarity within circuits – Obeys Rent.
Assumption: the complexity of the interconnection topology is equal at all levels.
Conclusion – Rent’s rule is a result of the design and synthesis.

45. Donath’s Hierarchical Placement Model
1. Partition the circuit
4 equal sized modules, with a minimal cut.
2. Partition the Manhattan grid
4 equal sized modules, with a minimal cut.
3. Map the modules to the grid
Arbitrary mapping.
Background – Donath wanted an upper bound for wire length – for wirability, delay and power.
Preious models assumed random placement – got huge over estimations – not correlated with the design.
Insignificant termination rules.
This method displays self-similarity.
4. Repeat recursively
Until each block is assigned to one cell.
Result – Rent’s parameters
W. E. Donath. Placement and Average Interconnection Lengths of Computer Logic.
IEEE Trans. on Circuits & Syst., vol. CAS-26, pp , 1979.

46. Donath’s length estimation model
For the i-th level:
There are
For each block there are:
Assuming two-terminal nets :
Lambda is the number of gate pitches per side of a single block. (square root of the number of gates per block)
Last formula: nets for I (blocks*nets per block) – nets for I-1.
The nets of the i-1 level must be substracted.
Nets for level i : ni=

47. Average interconnection length
The wires can be of two types A and D.
Taken from a SLIP 2001 tutorial by Dirk Stroobandt
LA =
LD =
Average: (2*a+d)/3 recall that lambda must be replaced with function of N.
For the overall – assume the globla level has N gates, meaning: sqrt(N) gate pitches per side.
The average: ri=
Overall :
equals

48. Results Donath
Scaling of the average length L as a function of the number of logic blocks N : L G 5 10 15 20 25 30 1
100
103
106
105
104
107
r = 0.7
r = 0.5
r = 0.3 N
Similar to measurements on placed designs.
Taken from a SLIP 1999 tutorial by Dirk Stroobandt

49. Donath’s Model - overview
Provides average net length based on the circuit’s size and Rent parameters.
Can provide a rough net length distribution.
Obvious limitations:
Uniform distribution.
Partitioning algorithm.
Two terminals nets only.
Assumes perfect similarity.
Uniform dist. – must be refined.
Partitioning – better be correlated with the actual partitioning.
Two terminals – can be normalized by the average fan out.
The rent’s exponents slightly differ at the levels and regions.
BUT – the bottom line – it was a ground breaking work !
It was good enough for quite a long time, and was much refined since.