1. 1 VLSI Design SMD154 LOW-POWER DESIGN Magnus Eriksson & Simon Olsson

2. 2 Today’s Topics Introduction Power consumption How to reduce power consumption Tools used In the future

3. 3 Introduction Why do we want to decrease power consumption? –The marked wants longer battery life, higher performance and smaller size for portable devices –Small embedded systems with a small power source that needs to have a long life time –Lower power consumption decreases working temperature of the device

4. 4 Introduction Higher performance and longer battery life is conflicting demands –Sophisticated design techniques is needed to meet both of them Power management is one of the most critical design issues –Meet the demands of the market –Keep the working temperature at a acceptable level

5. 5 Where is the power consumed? –Static power consumption –Short circuit power consumption –Dynamic power consumption

6. 6 Where is the power consumed? Static power consumption PULL-UP NETWORK PULL-DOWN NETWORK GND V dd inout GND

7. 7 Where is the power consumed? Short circuit power consumption PULL-UP NETWORK PULL-DOWN NETWORK GND V dd inout GND I short_circuit

8. 8 Where is the power consumed? Dynamic power consumption PULL-UP NETWORK PULL-DOWN NETWORK GND V dd inout GND I dynamic ßSwitching activity C out Switching capacitance V DD Supply voltage fFrequency

9. 9 Reducing dynamic power consumption Decreasing switching activity (ß) –Can be done by using specific algorithms and coding modes. –This is the easiest way for a designer to influence the power consumption. Decreasing switching capacitance (C out ) –Can be done by using shorter wires and smaller devices. –Can only be changed below gate level.

10. 10 Reducing dynamic power consumption Decreasing supply voltage (V DD ) –Has the biggest influence on dynamic power consumption. –Lower supply voltage results bigger delays. –The critical path must be reduced to make a lower supply voltage possible. Decreasing frequency (f) –Will reduce the performance. –Performance and power consumption must be balanced.

11. 11 Decreasing switching activity Different coding techniques –Fewer bit transitions between two states Boolean expressions simplification –Gate minimization Avoid glitches –Get rid off unnecessary transitions Power down modes –Turn off parts of that are not in use

12. 12 Different coding techniques Gray coding –Hamming distance of one –Used when a sequence is predictable FSMs Address busses –Makes full use of the bit-width 000100 101 111 110 001 011 010

13. 13 Different coding techniques Bus-inversion coding (BI) –Compare the previous and current word –Invert the data if it results in fewer transitions –A flag bit is used with the bus to indicate if the data is inverted or not –Suited for data busses Partial bus-inversion (PBI) –Divides the bus in different parts with its own flag –Suited for address busses

14. 14 Different coding techniques Sign magnitude –Uses only one bit for the sign in contrast too two’s complement –Result in fewer transitions when going from a positive to a negative number –Needs more logic to implement than two’s complement bnbn b n-1...b0b0 magnitude sign

15. 15 Boolean expressions simplification Minimize the number of gates to avoid unnecessary transitions Just minimize the number of gates is not optimal if the activity of the signals differ –One example Both expressions have the same number of gates If A have the highest transition activity Y is the better solution (A only affects two gates instead of three) X = AB + AC + CD Y = A(B + C) + CD

16. 16 Avoid glitches Glitches results in unnecessary transitions, glitching power loss Logic with a long depth are more prone to have glitches Flip-flops can be added to shorten the depth of the logic to minimize the influence of glitches

17. 17 Power down modes Power supply shut down –Turns of the power in an entire module –Reducing the power consumption in that part to zero Clock gating –Halts the clock signal and reduces dynamic power consumption to zero –There will still be leakage –Gating the clock will increase the clock skew

18. 18 Power down modes Memory partitioning –Shut down a part of the memory that is not used, no information is stored at the moment –Some method to know when a partition is used is needed –Memory usage spread out over several partitions can be a problem Flip-flop enable –Decreases switching activity of flip-flops that are disabled but the clock signal is still active at all the time

19. 19 Tools Two major categories –Power-analysis/estimation Estimates what parts of the design that will consume most power Lets the designer do high level optimizations in an early stage –Power-optimization Implements different power optimization techniques Can be done without the interaction of the designer

20. 20 Tools Used on different levels of the design –Behavior-level Not implemented in any commercial tools –RT-level Fast power estimations can be done due to the high abstraction level Clock gating can be implemented as a power optimization at this level

21. 21 Tools Used on different levels of the design (cont.) –Gate-level The power consumption can be estimated from the equation for dynamic power consumption Medium accuracy and speed –Transistor-level The result is very accurate both for power estimation and optimization Tools used at this level are not very popular due to; high runtime and that most vendors do not provide transistor level netlists

22. 22 Tools Cadence Encounter –Supports power optimizations, e.g. Clock gating Multi-supply voltage (voltage scaling) –See figure for complete low-power design flow

23. 23 Tools Synopsys power compiler –Used both for power analysis and power optimization –Power analysis can be done both on RT- and gate- level –Power optimizations that can be done are Clock gating Operand isolation Leakage optimization Etc.

24. 24 The future To meet the demands of higher performance and longer battery time new techniques are needed Leakage will be a bigger part of the total power consumption when smaller technologies are used