1. Electrical Characteristics of Logic Gates Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush

2. Outline TTL versions Electrical Characteristics Average maximum power dissipation Switching Characteristics DC Noise Immunity (Noise Margin) DC and AC Fan-out Speed × Power CMOS Versions Interfacing TTL and CMOS Logic Gate Buffers Open Collector Buffers 2 © 2010 Dr. Ashraf Armoush, An-Najah National University

3. TTL TTL : Transistor-Transistor Logic Two transistors are used to drive each output of each chip Based on bipolar npn or pnp transistors TTL compatible: means that the inputs and outputs of the equipment follow the common rules that apply to the inputs and outputs of all TTL gates TTL Family: – 74---XX : commercial version [0 – 70°C] – 54---XX : military version [-55 – 125°C] 3 © 2010 Dr. Ashraf Armoush, An-Najah National University

4. TTL Versions (subfamilies) 1.Standard TTL (74xx) [obsolete]  The oldest standard version (late 1960’s)  Propagation Delay = 10 ns 2.Low Power TTL (74Lxx)  Low power (compared to the original TTL logic family),  Very slow (Propagation Delay = 33 ns) 3.Schottky TTL (74Sxx) [obsolete]  Introduced in the early 1970’s.  High speed applications (Propagation Delay = 3ns)  Switching speed improvement 300% over standard TTL  Use Schottky diod between the base and collector of each transistor (prevent the transistor from going into deep saturation) 4.Low Power Schottky (74LSxx)  Low power (≈1/5 supply current).  Switching speed is comparable to the standard TTL (Propagation Delay = 10 ns) 4 © 2010 Dr. Ashraf Armoush, An-Najah National University

5. Electrical Characteristic High-level output voltage (V OH ): the minimum voltage on the output pin when the input condition establish logic HIGH at the output. LOW-level output voltage (V OL ): the maximum voltage on the output pin when the input condition establish logic LOW at the output. Low-level input voltage (V IL ): the maximum voltage applied at the input that is recognized as a legal LOW level. HIGH-level input voltage (V IH ): the minimum voltage that needs to be applied at the input to be recognized as a legal HIGH level. Output short circuit current (I OS ): It is a troubleshooting technique to short a high level output to ground temporarily to verify that a circuit is working correctly 5 © 2010 Dr. Ashraf Armoush, An-Najah National University

6. Electrical Characteristic 6 © 2010 Dr. Ashraf Armoush, An-Najah National University

7. Input Output Voltage Ranges 7 © 2010 Dr. Ashraf Armoush, An-Najah National University

8. DC Noise Immunity (Noise Margin) 8 © 2010 Dr. Ashraf Armoush, An-Najah National University V IH V IL V IH V IL V OH V OL V OH V OL

9. Open (floating) Pins If you leave a pin (floating), the gate will respond as if that pin were connected to a logic 1. Problem: It will act like a radio antenna.  any received noise can easily cause plus-sensitive circuits (such as flip-flops) to operate incorrectly. Solutions: 1.Connect two pins together. Disadvantages: – Increases the load current which will decrease the fan-out. – Doubles the capacitive 2.Connect them to Vcc 3.Connect them to Vcc through a pull-up resistor 4.Connect the unused input to an inverter output biased high. 9 © 2010 Dr. Ashraf Armoush, An-Najah National University

10. Open (floating) Pins 10 © 2010 Dr. Ashraf Armoush, An-Najah National University

11. Complementary Metal-Oxide Semiconductor (CMOS) Logic Circuits CMOS gates uses voltage-controlled complementary n- and p-channel MOS transistor. The important characteristics of CMOS devices are: – high noise immunity – low static power consumption. Slower than TTL but with smaller area (high density)  the vast majority of modern integrated circuit manufacturing is on CMOS processes. CMOS Families: – Metal gate CMOS (CD40XX) has a rated working voltage of 3 – 15 – Silicon gate CMOS (74CXX) logic has a working voltage range of 2 -6V 11 © 2010 Dr. Ashraf Armoush, An-Najah National University N-MOS P-MOS CMOS Inverter

12. CMOS Versions (subfamilies) 1.CD4000 Series  The oldest CMOS version (1968)  Operate over a wide range of V CC [3-15 V]  The poorest performance 2.CMOS (74Cxx) [obsolete]  The first of CMOS to be pin compatible with TTL (in the mid-1970s),  Twice as fast as CD4000 series 3.High Speed CMOS (74HC/HCTxx/)  Introduced in the early 1980s.  DC fan-out (20 CMOS or 10 TTL)  74HCT has electrical characteristic compatible to TTL (74LS)  74HCxx is 5 times faster than a 74Cxx (t PD = 9 ns) ≈ t PD for 74LSxx 4.Advanced CMOS (74AC/ACTxx)  Designed to be competitive with 74AS and 74ALS (late 1980’s)  Devices in this series are not pin compatible with their TTL counterparts.  Switching speed is comparable to the 74ALS family (t PD = 9 ns)  74ACTxx is designed to have TTL compatible V IH and V IL 12 © 2010 Dr. Ashraf Armoush, An-Najah National University

13. Recommended Operating Conditions CMOS can operate over a wide range of V CC [2 to 6 V] Many of the data sheet tests are specified at three values of V CC [2, 4.5 and 6 V] Ex: For V CC = 4.7V (standard) 74HC00 has: – V IH = 3.15V (problem with TTL interface) – V IL = 0.9 V 74HCT00 has: – V IH = 2.1V (TTL compatible) – V IL = 0.9 V 13 © 2010 Dr. Ashraf Armoush, An-Najah National University

14. Noise Immunity 74HC with V CC = 4.7V – V OH = 4.1V – V OL = 0.1 V – V IH = 3.15V – V IL = 0.9 V  V NH = V OH – V IH = 4.4 – 3.15 = 1.75 V  V NL = V IL – V OL = 0.9 – 0.1 = 0.8 V Both V NH and V NL are greter than those of its TTL counterpart. 14 © 2010 Dr. Ashraf Armoush, An-Najah National University

15. Interfacing TTL and CMOS Conditions for interfacing: -V OH ≥ V IH -V OL ≤ V IL -|I OH | > |I IH | -|I OL |> |I IL | 15 © 2010 Dr. Ashraf Armoush, An-Najah National University