1. EET 252 Unit 4 Programmable Logic: SPLDs & CPLDs  Read Floyd, Sections 11-1 to 11-4.  Study Unit 4 e-Lesson.  Do Lab #4.  Homework #4 and Lab #4 due next week.  Quiz next week.

2. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Programmable Logic SPLD (Simple PLD): the earliest type of array logic used for fixed functions and smaller circuits with a limited number of gates. (The PAL and GAL are both SPLDs). CPLD (Complex PLD): contain multiple SPLD arrays and inter- connection arrays on a single chip. FPGA (Field Programmable Gate Array): a more flexible arrangement than CPLDs, with much larger capacity. Programmable Logic Devices (PLDs) are chips with a large number of gates and flip flops that can be configured with software to perform a specific logic function or perform the logic for a complex circuit. Major types of PLDs are:

3. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Programmable Logic Advantages of PLDs over fixed-function chips include  Reduced complexity of circuit boards Lower power requirements Less board space Simpler testing procedures  Higher reliability  Design flexibility

4. Approximate Equivalent Densities  The Lattice GAL22V10 (a popular SPLD) is equivalent to about 500 logic gates.  A typical Altera MAX7000 CPLD is equivalent to about 2500 logic gates.  A typical Altera Cyclone FPGA is equivalent to about 50,000 gates.

5. Major PLD Manufacturers  Three big names in this field are Xylinx, with 51% of market share Altera, with 34% Lattice, with less than 10%  Market share numbers retrieved from Wikipedia on 10/26/2011. Wikipedia

6. Some Product Lines from Altera and Xylinx  Altera CPLDs: MAX FPGAs: Cyclone, Arria, Stratix Programming software: Quartus II  Xylinx: CPLDs: CoolRunner, XC9500 FPGAs: Vertix, Spartan, Kintex, Artix Programming software: ISE

7. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed PALs and GALs PALs have a one-time programmable (OTP) array, in which fuses are permanently blown, creating the product terms in an AND array. All PLDs contain arrays. Two important kinds of SPLD are PALs (Programmable Array Logic) and GALs (Generic Array Logic). A typical array consists of a matrix of conductors connected in rows and columns to AND gates. Simplified AND-OR array X A A B B

8. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed X A A B B What function is represented by the array? The function represents an XOR gate. X = AB + AB PALs are programmed with a specialized programmer that blows selected internal fuse links. After blowing the fuses, the array represents the Boolean logic expression for the desired circuit. PALs

9. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The GAL (Generic Array Logic) is similar to a PAL but can be reprogrammed. For this reason, they are useful for new product development (prototyping) and for training purposes. A A B B X GALs were developed by Lattice Semiconductor. GALs

10. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed PALs and GALs are often represented by simplified diagrams in which a single line represents multiple gate inputs. The logic shown is for the XOR gate, given previously. Input buffer A A B B Single line with slash indicating multiple AND gate inputs Fuse blown Fuse intact AB AB + AB PALs and GALs

11. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The AND-gate arrays in PALs and GALs connected to macrocells. A macrocell is an OR gate together with associated output logic. Two types of PAL/GAL macrocells are shown. For these particular macrocells, the I/O pin can serve as an input or an output. Tristate control From AND array I/O Programmable fuse link to control output polarity To AND array PALs and GALs

12. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed The GAL22V10 is a typical SPLD. It has 12 dedicated inputs pins and 10 pins that can be used as inputs or outputs. Link to datasheet GAL22V10

13. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed CPLDs A complex programmable logic device (CPLD) has multiple logic array blocks (LABs), each roughly equivalent to an SPLD. LABs are connected via a programmable interconnect array (PIA). Various CPLDs have different structures for these elements. The PIA is the interconnection between the LABs.

14. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed CPLDs The architecture of a CPLD is the way in which the internal elements are configured. A portion of the Altera MAX 7000 series is shown. This structure is typical for CPLDs, but densities and features (macrocells, etc) will vary between manufacturers. I/O pins General-purpose inputs

15. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed CPLDs Macrocells in the Altera MAX 7000 series can generate up to five product terms. For expressions requiring more terms, the output can be expanded as described in the text. Expander example

16. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed CPLD Macrocells In addition to combinational logic, many macrocells have registered outputs available (using programmable flip- flops). This allows the CPLD to perform sequential logic.

17. Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 11.24 Commonly used symbol for a multiplexer. It can have any number of inputs.

18. Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 11.25 A macrocell in the Altera MAX 7000 family of CPLDs.

19. Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 11.26 A macrocell configured for generation of an SOP logic function. Red indicates data path.

20. Copyright ©2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. Digital Fundamentals, Tenth Edition Thomas L. Floyd Figure 11.27 A macrocell configured for generation of a registered logic function. Red indicates data path.

21. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Programmable Logic Software All manufacturers of programmable logic provide software to support their products. The process is illustrated in the flowchart. The first step is to enter the logic design into a computer. It is done in one of two ways: 1) Schematic entry 2) Hardware description language (HDL).

22. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Programmable Logic Software In schematic entry, the design is drawn on a computer screen by placing components and connecting then with simulated wires. After drawing the schematic, it can be reduced to a single block symbol:

23. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Functional Simulation After entering the circuit, the circuit is tested in a functional simulation. You can test the circuit with waveforms to verify the operation. The following shows the functional test of a counter using a waveform editor:

24. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Synthesis After the simulation, the computer program optimizes the logic by eliminating redundant terms and generating a netlist, (a connection list) that is a complete description of the circuit. Netlist

25. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Implementation The computer next “maps” the design from the netlist to fit it to a target device. Data for all potential target devices are in a software library. The computer must account for the I/O pins and fit the logic to the target device.

26. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Timing Simulation After implementation, a timing simulation is done that takes into account the specific delays in the target device and verifies that there are no problems with the timing. As in the case of the functional simulation, the waveform editor can be used to review final timing. If a problem is revealed, it is not too late to correct it before downloading the file.

27. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Device Programming The final step is to send the programming file from the computer to the target device and test the implementation. Shown is a PLDT-2 prototyping board with an Altera PLD as the target device. Connections are added to the board from a pulse generator and oscilloscope to test the actual circuit in a laboratory environment. The prototyping board has built-in power supplies, interfacing, I/O, and more.

28. © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10 th ed Selected Key Terms PAL GAL Macrocell CPLD A type of one-time programmable SPLD that consists of a programmable array of AND gates that connects to a fixed array of OR gates. A reprogrammable type of SPLD that that is similar to a PAL except it uses a reprogrammable process technology, such as EEPROM instead of fuses. Part of a PAL, GAL, or CPLD that generally consists of one OR gate and some associated output logic. A complex reprogrammable logic device that consists basically of multiple SPLD arrays with programmable interconnections.