1. September 22, 2005 ESF Workshop-Perugia 1 Virgo Control Electronic upgrade Annecy/Pisa/EGO B.Mours

2. September 22, 2005 ESF Workshop-Perugia 2 Post C6 upgrades (I) Sensitivity from Aug 12 (End of C6) Sensitivity from Aug 27 Improvement due to Linear Alignment (4 loops closed instead of 2) DAC noise reduction PR z control noise reduction (Neo filter with roll-off @ 100 Hz) BS z control noise : alpha tuning New optical setup for B5  Reduction of laser frequency noise 2kHz bump due to detection tower pump (exciting external bench resonances)

3. September 22, 2005 ESF Workshop-Perugia 3 Current main Virgo control loop l Frequency: 10 kHz  100µs  30 VME crates for this loop l Main limitations:  Old hardware (~10 years old)  DSP and CPU performances –Time is shared between l Computing l Interrupt response l Data access (on VME bus : ~ 3-4 words/µs + 3 µs) »Input, Output, Monitoring – fitting complex filters or algorithms ?  Delay (distributed system): AR Filter+Pr+GC+Sc+Filter  500 µs –Impact on the loop bandwidth  Sampling rate of the dark port and monitoring channel (20kHz) –Fast readout could be useful for debugging  Analog servo for the frequency stabilization Detec tion Laser Nd:YAD P:20W, :1.064  m West End North End West Input Recyc ling North Input Bea m Spli tter IMC Control ITF Control 3Km3Km Fabry-Perot Cavity (F:50, L’:100Km) Recycling Cavity (P:1Kw) Output Mode- Cleaner Input Bench Input Mode- Cleaner ( L:150m) OMC Control Timing

4. September 22, 2005 ESF Workshop-Perugia 4 Redesign of the control Electronic l Increase  Computing performances: new DSP and CPU  Data throughput: new DOL –gain a factor 10: 100Mbits/s  1 Gbits/s)  Lower Noise: New ADC, DAC, differential connection (ADC, timing)  More channels: more compact electronic l New timing system  To be interfaced to the new boards  distribute the GPS signal: simpler l A possible goal for the main loop: 60 kHz  1/60k=16us = Arm length l Will increase the DAQ rate  Now 18 MB/s (6-7 MB/s of compressed data) –Front end, preprocessing, data transport, storage

5. September 22, 2005 ESF Workshop-Perugia 5 New processing board l Replace 5 VME boards by 1:  1 VME CPU:  PC 104 or PC on PMC  2 Digital Optical Link+1 Timing:  TOLM  1 DSP board  DSP mezzanine l To be used by Pr, GC, Sa, Sc… l Payoff: Integrated DAQ (frame building)

6. September 22, 2005 ESF Workshop-Perugia 6 New DSP Mezzanine 1 DSP @ 60 MHz (60 MFLOPS peak)  6 DSP’s @ 100MHz (ADSP211160N SHARC DSP; 3.4 GFLOPS) DSPV03A Functional Blocks Diagram VME PCI DSP Local Bus VSB DSP #1 DSP #2 DSP #3 DSP #4 DSP #5 DSP #6 Flash Memory LB2VSB Bridge PCI2LB Bridge PCI2VME Bridge PCI Bridge CPU Module Fast Ethernet Console DOL Timing Dual Port Memory Front Panel Serial link 4 4 22 Link Port 4 3

7. September 22, 2005 ESF Workshop-Perugia 7 MDSPAS – Top View DSP 1 234 56 AM FPGA B Dual Port Memory  A prototype exist since a few weeks

8. September 22, 2005 ESF Workshop-Perugia 8 TOLM l TOLM  Timing and Optical Link Mezzanine l Interfaces:  PCI interface for configuration and tests  TIMING part: –1PPS and GPS on differentiel link (one single cable; RJ45) l Changed to IRIG-B on coax cable + fibers. –1 Serial link to DSP for GPS time info –2 front panel output for pulses –2 DPS output for pulses  Digital Optical Link part –2 input and output fibers l Monomode or multimodes l Higher data rate: 155Mbits/s  1GBits/s –4 DSP links (PCI-J4) l Status:  Prototype available since last September  Developing the FPGA software and testing.

9. September 22, 2005 ESF Workshop-Perugia 9 Timing generation l The TOLM use always a local oscillator (TCXO) l The local oscillator will be lock on a GPS reference l Need:  Distribution of GPS clock + absolute timing information: IRIG-B l Selection of clock and distribution boards:  In progress 3.3 Km max. 3 m max Optic FibersCoax cable GPS Antenna Commercial GPS Clock Copper to Fiber TOLM Fiber to coper IRIG-B

10. September 22, 2005 ESF Workshop-Perugia 10 Optical Link: Extension board l Need Fan-out board in the case of  Global control connections  Multiple Pr/ADC input l Multiple inputs(8)/single output l Single input/ Multiple outputs l Need simple protocol to route the data l Development: started Extension Board 1 2 3 M TOLM Carte PC Carte DSP Link Port Processing Board TOLM Carte PC Carte DSP Link Port Processing Board Suspension 1 Suspension 2 Pr/ADC N 2 1 N 2 1 Extension Board 1 2 3 M TOLM Carte PC Carte DSP Link Port Processing Board

11. September 22, 2005 ESF Workshop-Perugia 11 New ADC/DAC l New ADC:  More bits (18?)  Faster sampling rate (100 kHz – 1 MHz)  Input compression (whitening) filters  On board decompression option  Low noise: Optical link to processing boards  Include (part of) the TOLM design for timing generation?  Versatile enough to reduce the number of ADC type (Currently 3). l New DAC  Need of a very high dynamical range for actuators.  The DAC board used has -98 dB of total harmonic distortion + noise –while newer chips are available on market with –120 dB  Two different design approaches are under evaluation –Standard VME board, 16 ch. 24bits (nominal) –Distributed system l Status:  Early design phase (selecting the main components)

12. September 22, 2005 ESF Workshop-Perugia 12 Conclusion l Development of the new control system is in progress l It will be a MAJOR change for Virgo  Hardware and Software  Probably several weeks of down time in 2007 (?)