1. Design Technical Working Group 4 April 2003 - Work In Progress – Not for Publication Design Technical Working Group Spring Meeting 2003 uUS oAndrew Kahng, UC San Diego (Telephone) uJapan oYamamoto-san (Telephone) uEurope oRalf Brederlow, Infineon oMaarten Vertregt, Philips oJosef Sauerer, FhG oPeter Schwarz, FhG

2. Design Technical Working Group 4 April 2003 - Work In Progress – Not for Publication Revisions for ITRS 2003 System Drivers Chapter –New material Embedded memory sub-chapter –Improvements to existing material SOC-centric chapter reorganization include SIP in multi technology integration timeline Design Chapter –Seamless design flow (System and Circuit EDA including AMS and other styles for SoC/SiP design) –Refinement of design cost model –Prepare Revision of Design Chapter (treat issues once, align with System Drivers Chapter)

3. Design Technical Working Group 4 April 2003 - Work In Progress – Not for Publication x = a + b + c + d + e + f + g + h + i ; Higher Level of Abstraction Define # of Adders and Order of Calculation Constraint = Power, Speed, Area RTL (Less productive but more exact) Result A # of Adders = 1 Speed = 9 Clocks Result B # of Adders = 2 Speed = 5 Clocks RTL Synthesis will automate the RTL design task. Example: dealing with Productivity Gap

4. Design Technical Working Group 4 April 2003 - Work In Progress – Not for Publication Example: System and Circuit EDA for AMS Executable specification, A/MS description languages: VHDL-AMS, Verilog-AMS, SystemC-AMS, … Circuit synthesis Design validation: simulation and formal verification Layout synthesis, incl. RF and interconnect-driven Design for manufacturability, yield enhancement IP re-use