1. Work in Progress --- Not for Publication Japan Taiwan US Ken Monnig Christopher Case Europe Hans-Joachim Barth Dirk Gravesteijn Korea ITWG Meeting

2. Work in Progress --- Not for Publication Key Issues - Interconnect PMD not described in roadmap M0, M1 and local wiring need clarification and definition Alternative memory needs in the back end System level solutions required Cu resistivity increase impact appears ~2006 – need replacement for resistivity metric

3. Work in Progress --- Not for Publication Key Issues – Interconnect (2) Extended hierarchical wiring Replace bulk low k < with ~ Divide 3D interconnect into two sections that cover topics such as active, passive, emerging devices, post-passivation signal redistribution layer etc. From Japan - k should be derived from design/system requirement. It should be clearly described how the k- values have been derived.