1. 1 Feb19, 2003 ITRS 2003, Sunnyvale, Ca ITRS Conference April 3-4, 2003 Amsterdam, Netherlands ITRS 2003 Yield Enhancement TWG Attendees: Mike Retersdorf (International Sematech/AMD), Ines Thurner (Infinion), Andreas Nutsch(Fraunhofer), Mike Patterson( Intel), Chris Muller(Purafil), Richard Corel(Purafil), Andreas Neuber (M + W Zander), Dick Verkleij (Philips)

2. 2 Feb19, 2003 ITRS 2003, Sunnyvale, Ca Key Challenges High Aspect Ratio inspection and review Signal/Noise: real vs nuisance defects. Methods/tools for faster Yield learning. Ability to measure WECC purity levels and their correlation to yield. Wafer edge inspection

3. 3 Feb19, 2003 ITRS 2003, Sunnyvale, Ca Yield Enhancement TWG status Major Updates –Incorporated 300mm wafer size. –Focus on automatic defect classification (ADC). –Extensive benchmarking ongoing to validate 2003 node for WECC (Wafer environment contamination control) –Extensive rework on table for WECC. Major Discussion –Backside contamination for inspection and product wafer specification –Need of copper update for wafer environment? –Defining requirements on AMC(Airborne molecular contamination)

4. 4 Feb19, 2003 ITRS 2003, Sunnyvale, Ca Cross TWG discussion FEP –Edge exclusion requirements on 2 than 1mm also on process tools? –Align of front side particle specification in FEP chapter to particle budget table in YE chapter. –Input on all impurity level in WECC. Litho –need measure of Depth of focus for backside inspection specification. –Input on AMC level and purge gas in WECC discussion completed further exchange via email. –No resist purity covered by YE. Factory Integration –Ensure vibration, ESD, and RF are covered. Design –Close loop between design and Yield learning.