1. Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 39: December 6, 2013 Repeaters in Wiring (maybe: Transmission Line Scenarios)

2. Previously Transmission line (LC wire) wire delay scales as Length Unbuffered RC wire delay scales as Length 2 –0.5 R wire C wire –0.5 L 2 R u C u Penn ESE370 Fall2013 -- DeHon 2

3. Today RC (on-chip) Interconnect Buffering maybe –Transmission Line Scenarios Penn ESE370 Fall2013 -- DeHon 3

4. Back to RC Wire (on-chip, no inductance, L) Penn ESE370 Fall2013 -- DeHon 4

5. Delay of Wire Long Wire: 1mm R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) Driven by inverter –R 0 = 25K  –C 0 = 0.01 fF –Assume velocity saturated, sized W p =W n =1 Loaded by identical inverter Penn ESE370 Fall2013 -- DeHon 5

6. Formulate Delay Penn ESE370 Fall2013 -- DeHon 6 Delay of inverter driving wire? Should be able to do these calculations on final.

7. Calculate Delay C load = 2 C 0 R buf = R 0 C self =  2 C 0 = 2 C 0 Penn ESE370 Fall2013 -- DeHon 7

8. Buffering Wire Complete Preclass Table Penn ESE370 Fall2013 -- DeHon 8

9. N Buffers Delay Equation for N buffers? Penn ESE370 Fall2013 -- DeHon 9

10. Minimize Delay How determine N to minimize delay? Derivative with respect to N Penn ESE370 Fall2013 -- DeHon 10

11. Solve for N Penn ESE370 Fall2013 -- DeHon 11

12. Minimize Delay Penn ESE370 Fall2013 -- DeHon 12 Equalizes delay in buffer and wire

13. Calculate: Delay at Optimum Stages for Example R wire = 60K  for the 1mm) C wire = 0.16 pF  for the 1mm) R buf =R 0 = 25K  C self =C load =2(C 0 = 0.01 fF)=0.02fF Penn ESE370 Fall2013 -- DeHon 13

14. Segment Length R wire = L×R unit C wire = L×C unit Penn ESE370 Fall2013 -- DeHon 14

15. Optimal Segment Length Delay scales linearly with distance once optimally buffered Penn ESE370 Fall2013 -- DeHon 15

16. Buffer Size? How big should buffer be? –R buf = R 0 /W –C load = 2 W C 0 (assuming velocity saturation) –C self =  2 W C 0 Penn ESE370 Fall2013 -- DeHon 16

17. Implication W R wire = L×R unit C wire = L×C unit  W independent of Length –Depends on technology Penn ESE370 Fall2013 -- DeHon 17

18. Delay at Optimum W With  =1, 1+  =2 Same size as first term Penn ESE370 Fall2013 -- DeHon 18

19. Ideas Wire delay linear once buffered Optimal buffering matches –Buffer delay –Delay on wire between buffers Penn ESE370 Fall2013 -- DeHon 19

20. Final Everything –Including today Focus on wiring, memory –Crosstalk –Transmission lines Delay Energy Static CMOS Precharge Pass Transistors Ratio Clocking Restoration Buffering Penn ESE370 Fall2013 -- DeHon 20 2010, 2011, 2012 finals all good content --2011 many “small” problems – good coverage

21. Admin Spencer Review Monday (12/9) –Talk with him about final Q&A session on Wednesday or Thursday Final (12/13) noon Towne 307 Real Genius (Saturday 12/14 2pm) –Levine 307 Penn ESE370 Fall2013 -- DeHon 21

22. Transmission Line Scenarios (time permitting) Penn ESE370 Fall2013 -- DeHon 22

23. Transmission Line Data travels as waves Line has Impedance May reflect at end of line Penn ESE370 Fall2013 -- DeHon 23

24. Bus Common to have many modules on a bus –E.g. PCI slots –DIMM slots for memory High speed  bus lines are trans. lines Penn ESE370 Fall2013 -- DeHon 24 http://en.wikipedia.org/wiki/File:DIMMs.jpg

25. Multi-drop Bus Ideal –Open circuit, no load Penn ESE370 Fall2013 -- DeHon 25

26. Multi-Drop Bus Impact of capacitive load (stub) at drop? –If tight/regular enough, change Z of line Penn ESE370 Fall2013 -- DeHon 26

27. Multi-Drop Bus Long wire stub? –Looks like branch may produce reflections Penn ESE370 Fall2013 -- DeHon 27

28. What happens at branch? Penn ESE370 Fall2013 -- DeHon 28

29. Branch Transmission line sees two Z 0 in parallel –Looks like Z 0 /2 Penn ESE370 Fall2013 -- DeHon 29

30. Z 0 =50, Z 1 =25 At junction: –Reflects V r =(25-50)/(25+50)V i –Transmits V t =(50/(25+50))V i Penn ESE370 Fall2013 -- DeHon 30

31. End of Branch What happens at end? If ends in matched, parallel termination –No further reflections Penn ESE370 Fall2013 -- DeHon 31

32. Branch Simulation Penn ESE370 Fall2013 -- DeHon 32

33. Branch with Open Circuit? What happens if branch open circuit? Penn ESE370 Fall2013 -- DeHon 33

34. Branch with Open Circuit Reflects at end of open-circuit stub Reflection returns to branch –…and encounters branch again –Send transmission pulse to both Source and other branch Sink sees original pulse as multiple smaller pulses spread out over time Penn ESE370 Fall2013 -- DeHon 34

35. Open Branch Simulation Penn ESE370 Fall2013 -- DeHon 35

36. Open Branch Simulation Penn ESE370 Fall2013 -- DeHon 36

37. Impedance Change What happens if there is an impedance change in the wire? Z 0 =75 , Z 1 =50  –What reflections and transmission do we get? Penn ESE370 Fall2013 -- DeHon 37

38. Z 0 =75, Z 1 =50 At junction: –Reflects V r =(50-75)/(50+75)V i –Transmits V t =(100/(50+75))V i Penn ESE370 Fall2013 -- DeHon 38

39. Impedance Change Z 0 =75, Z 1 =50 Penn ESE370 Fall2013 -- DeHon 39

40. Idea Transmission lines –high-speed –high throughput –long-distance signaling Termination Signal quality Penn ESE370 Fall2013 -- DeHon 40

41. Admin Spencer Review Monday (12/9) –Talk with him about final Q&A session on Wednesday or Thursday Final (12/13) noon Towne 307 Real Genius (Saturday 12/14 2pm) –Levine 307 Penn ESE370 Fall2013 -- DeHon 41