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EE141 © Digital Integrated Circuits 2nd Introduction 1 EE4271 VLSI Design Dr. Shiyan Hu Office: EERC 518 shiyan@mtu.edu Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Introduction
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EE141 © Digital Integrated Circuits 2nd Introduction Class Time and Office Hour Class Time: MWF 16:05-16:55 (EERC 214) Office Hours: MWF 15:00-16:00 or by appointment, office: EERC 518 Textbook (required): Digital Integrated Circuits: A Design Perspective, second edition, by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Prentice Hall, 2003. or CMOS VLSI Design: A Circuits and Systems Perspective, fourth edition, by Neil H.E. Weste and David M. Harris, Addiuson Wesley, 2009 Grading: Homework 20% Midterm 20% Final 30% Lab 30% 2
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EE141 © Digital Integrated Circuits 2nd Introduction Course Website http://www.ece.mtu.edu/faculty/shiyan/EE4271Fall13.htm Contact information of instructor Email: shiyan@mtu.edushiyan@mtu.edu EERC 518 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyanhttp://www.ece.mtu.edu/faculty/shiyan 3
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EE141 © Digital Integrated Circuits 2nd Introduction 4 What is this course all about? Introduction to digital integrated circuits. CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinatorial Circuits and Sequential circuits. Computer-Aided Design. What will you learn? Understanding, designing, and optimizing digital circuits with respect to different quality metrics: speed, power dissipation, cost, and reliability
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EE141 © Digital Integrated Circuits 2nd Introduction 5 Agenda Introduction: Issues in digital integrated circuit (IC) design Device: MOS Transistors Wire: R, L and C Fabrication process CMOS inverter Combinational logic structures Sequential logic gates Design methodologies VLSI Computer-Aided Design Timing/power optimizations on gate and interconnect
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EE141 © Digital Integrated Circuits 2nd Introduction 6 Introduction Why is designing digital ICs different today than it was before? What is the challenge?
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EE141 © Digital Integrated Circuits 2nd Introduction The Transistor Revolution First transistor Bell Labs, 1948
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EE141 © Digital Integrated Circuits 2nd Introduction The First Integrated Circuit First IC Jack Kilby Texas Instruments 1958
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EE141 © Digital Integrated Circuits 2nd Introduction 9 Intel 4004 Micro-Processor Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation
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EE141 © Digital Integrated Circuits 2nd Introduction Intel 8080 Micro-Processor 1974 4500 transistors
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EE141 © Digital Integrated Circuits 2nd Introduction 11 Intel Pentium (IV) microprocessor 2000 42 million transistors 1.5 GHz
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EE141 © Digital Integrated Circuits 2nd Introduction Modern Chip
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EE141 © Digital Integrated Circuits 2nd Introduction 13 Moore’s Law lIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
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EE141 © Digital Integrated Circuits 2nd Introduction Moore’s law Twice the number of transistors, approximately every two years
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EE141 © Digital Integrated Circuits 2nd Introduction 15 Moore’s Law Electronics, April 19, 1965.
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EE141 © Digital Integrated Circuits 2nd Introduction 16 Transistor Counts 1,000,000 100,000 10,000 1,000 10 100 1 19751980198519901995200020052010 8086 80286 i386 i486 Pentium ® Pentium ® Pro K 1 Billion Transistors Source: Intel Projected Pentium ® II Pentium ® III Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 17 ITRS Prediction
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EE141 © Digital Integrated Circuits 2nd Introduction 18 Moore’s law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Transistors on Lead Microprocessors double every 2 years Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 19 Frequency P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 1000 10000 19701980199020002010 Year Frequency (Mhz) Lead Microprocessors frequency doubles every 2 years Doubles every 2 years Courtesy, Intel Not true any more!
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EE141 © Digital Integrated Circuits 2nd Introduction 20 0.18 Source: Gordon Moore, Chairman Emeritus, Intel Corp. 0 50 100 150 200 250 300 Technology generation ( m ) Delay (psec) Transistor/Gate delay Interconnect delay 0.80.50.25 0.15 0.35 Interconnects Dominate
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EE141 © Digital Integrated Circuits 2nd Introduction 21 Power Dissipation P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 197119741978198519922000 Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 22 Power is a major problem 5KW 18KW 1.5KW 500W 4004 8008 8080 8085 8086 286 386 486 Pentium® proc 0.1 1 10 100 1000 10000 100000 19711974197819851992200020042008 Year Power (Watts) Power delivery and dissipation will be prohibitive Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 23 Power density 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel
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EE141 © Digital Integrated Circuits 2nd Introduction 24 Not Only Microprocessors Digital Cellular Market (Phones Shipped) 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Power Management Small Signal RF Power RF (data from Texas Instruments) Cell Phone
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EE141 © Digital Integrated Circuits 2nd Introduction 25 Many Chips
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EE141 © Digital Integrated Circuits 2nd Introduction 26 Challenges in Digital Design Ultra-high speed design Interconnect delay Reliability, Manufacturability Power Dissipation Time to market
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EE141 © Digital Integrated Circuits 2nd Introduction 27 Productivity Trends 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 200319811983198519871989199119931995199719992001200520072009 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Source: Sematech Complexity outpaces design productivity Complexity Courtesy, ITRS Roadmap
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EE141 © Digital Integrated Circuits 2nd Introduction 28 Computer-Aided Design Every new generation can integrate 2x more functions per chip Chip price does not increase significantly Cost of a function decreases by 2x However, Design engineering population does not double every two years. How to design much more complex chips (with more and more functions)? Great need for ultra-fast design methods Design Automation (Computer-Aided Design)
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EE141 © Digital Integrated Circuits 2nd Introduction 29 Design Abstraction Enables CAD n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
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EE141 © Digital Integrated Circuits 2nd Introduction 30 Design Metrics How to evaluate performance of a digital circuit (gate, block, …)? Speed (delay, operating frequency) Power dissipation Cost –Design time –Design effort Reliability –Process, voltage and temperature variations
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EE141 © Digital Integrated Circuits 2nd Introduction 31 Cost of Integrated Circuits NRE (non-recurrent engineering) costs design time and effort to design layout and mask one-time cost factor Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area
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EE141 © Digital Integrated Circuits 2nd Introduction 32 NRE Cost is Increasing
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EE141 © Digital Integrated Circuits 2nd Introduction 33 Die Cost Single die Wafer From http://www.amd.com Going up to 12” (30cm)
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EE141 © Digital Integrated Circuits 2nd Introduction 34 Yield
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EE141 © Digital Integrated Circuits 2nd Introduction 35 Defects is approximately 3 in the current fabrication process About 0.5-1 defect per cm 2.
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EE141 © Digital Integrated Circuits 2nd Introduction 36 Some Examples (1994) ChipMetal layers Line width Wafer cost Def./ cm 2 Area mm 2 Dies/ wafer YieldDie cost 386DX 20.90$9001.04336071%$4 486 DX2 30.80$12001.08118154%$12 Power PC 601 40.80$17001.312111528%$53 HP PA 7100 30.80$13001.01966627%$73 DEC Alpha 30.70$15001.22345319%$149 Super Sparc 30.70$17001.62564813%$272 Pentium 30.80$15001.5296409%$417
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EE141 © Digital Integrated Circuits 2nd Introduction 37 Summary Digital integrated circuit design faces huge challenges for the coming decades High speed Low power Short design time for highly complex circuit having 1 billion transistors Reliable under noise and variations Purpose of the course Understand the basics of VLSI design Getting a clear perspective on the challenges and potential solutions
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