1. SYSC 2001* A Foundations of Computer Systems Fall 2006
Section A: Prof. Pearce
Room VS (VSIM)
(613) x 4054

2. Course Objectives how computers work as machines.
how computers have been engineered to improve performance.
reinforce basic programming concepts learned in first year courses.
pre-requisite knowledge for SYSC 2003* and SYSC 3601*

3. Scope device underlying components of the computer
how the components function
machine language programming  software control
originated in the 1940's, endured to modern day.
    .
Processor
Memory
Input/Output
device
Bus

4. Scope (more) major enhancements  engineered for performance
net execution speed, cost, power
improvements enabled by transistor technology
increasing numbers in components
improvements presented in this course deal with modifications to how the components function
not transistor technology

5. Scope (more) several processor families are used as examples
Intel IA (80x86 family) and Motorola PowerPC
Cell Processor ??
relationship between high level structured programming languages and machine languages  

6. Emphasis
how a computer supports the execution of instructions and external interactions
a roadmap to the engineering of performance in computers
short sequences of assembly language code fragments
expose concepts and issues where relevant
this course includes rudimentary programming at the machine and assembly code level,
but does not emphasize application concerns in how to program a computer, the synthesis of programs to solve problems, and software development concerns.

7. BUZZ, BUZZ, BUZZ, …. Intel® Celeron® D Processor 2.66GHz
533MHz FSB, 256KB L2 cache
256MB DDR SDRAM at 400MHz
Intel® Pentium® 4 Processor w/HT Technology (2.80GHz,800FSB)
512MB Dual Channel DDR2 SDRAM at 400MHz
128MB PCI Express™ x16 ATI Radeon X300
multicore?

8. PlayStation 3 key !!! SPEs: 6? 7? 8? 256K local memory RISC
from:
key !!!
PlayStation 3
SPEs:
6? 7? 8?
256K local memory
RISC
vector processing

9. Cell BE Processor EIB: 4 DMA rings
from:
Cell BE Processor
EIB: 4 DMA rings

10. Text William Stallings, “Computer Organization & Architecture”,
7th Edition, Prentice Hall,   Text Coverage: Chapters 1 – 5, 7, 9 – 12
  Additional course notes may be distributed on the course web page to supplement the text.
previous years have used 6th Edition – it is OK too

11. Expectations Of Learning
WARNING! Course Language Spoken Here ! 
course material includes, but not limited to, all indicated sections of text
lectures cover highlights of the material, but not necessarily all required sections
lectures and lab may supplement text with additional course material
STUDENTS are responsible for learning
relevant sections of the text should be read before they are discussed in class.    

12. Course Web Page course web page:

13. Prerequisite ECOR 1606* or SYSC 1102*
prerequisite waivers will not be granted to students who have not passed (or received advanced standing for) the prerequisite course.
no prerequisite? must withdraw by the last date for registration in Fall term courses
if not, you will be de-registered before the end of term

14. Assignments and Laboratory
at least five graded assignments
assignments, due dates, and submission instructions posted on the course web page.
late assignment?  valid medical certificate.
lab is open whenever the building is open
Labs: MC & 6055 MC
use the lab at any time, except when reserved for others
Tutorial lab sessions are scheduled so that you may meet with the TAs for assistance. 

15. Plagiarism? discuss design issues when working on assignments
BUT … write your own programs
Completing the assignments is one of the best ways of learning the material.
If you resort to copying  not likely to do well on the mid-term or final exam.
fine line between co-operating with colleagues (discussing problems and ideas) and copying (plagiarism).

16. Plagiarism ! Suspected plagiarism will be investigated !
may result in a mark of zero for the assignment
alleged instructional offences will be reported to the Associate Dean of Engineering
 see "Instructional Offences" in the Calendar

17. Exams
one closed book, no calculators permitted mid-term test Thursday, Oct. 25 – rooms TBA
Absence from the mid-term test will result in a mark of zero for the mid-term, unless a valid reason is documented and presented to the course professor within one week of the mid-term
miss mid-term?  make up at discretion of course prof.
closed book, no calculators permitted final exam during the University's formal examination period in December.
marked final exams will not be shown to students

18. Grading Scheme
To pass the course, a student must pass the final exam AND obtain an overall passing average (assignments plus midterm plus final exam).
if pass the final exam  final grade calculation: Assignments: 10 % Mid-term test: 25 % Final exam: 65 % 

19. Deferred Exam
Students who write a deferred examination (see the Undergraduate Calendar for regulations on deferred exams) have additional months to study and a less crowded examination schedule compared to their colleagues who write the final exam in December. As such, it is only fair to expect substantially better performance from these students on the deferred examination than on the December final exam.

20. Students with Disabilities
Students with a disability requiring academic accommodations:
please contact a coordinator at the Paul Menton Centre
complete the necessary letters of accommodation.
After registering with the PMC, make an appointment to meet with me at least two weeks prior to the mid-term test to discuss your needs.
This is necessary to ensure sufficient time to make the necessary arrangements.
Please note that the deadline for submitting completed forms to the PMC in this course is November 9.

21. Assignment 1 Posted on web site (like all assignments)
Due: See web site (assignment 1 is due very soon!)   See Appendix A (Number Systems) of the Stallings text.
Appendix A might not give enough info to complete the assignment. Maybe try:
too much info??

22. Course Content
admin details, discuss handout, introduction: September 6
Ch. 1
brief history of computers, design for performance, Pentium and PowerPC family evolution
Ch. 2
computer functions: instruction fetch/execute, interrupts, I/O

23. Course Content Ch. 3 ( plus appendix 3A on timing diagrams)
bus interconnection structures, simple timing diagrams
PCI bus
Ch. 4
memory system characteristics, memory hierarchy, intro to cache memory
cache memory design: size, mapping, replacement, write policy, number of caches
Pentium 4 and PowerPC examples

24. Course Content Ch. 5 internal memory types, organization
error correcting memory
DRAM: synchronous, cache
Ch. 7
I/O modules
programmed I/O
interrupt driven I/O
DMA, FireWire

25. Course Content midterm includes Ch 1 – 5, 7 Ch. 9
ALU, integer representation
integer arithmetic
IEEE floating point representation and arithmetic
Ch. 10 (plus Appendix 10B on endian and bit order)
instruction set characteristics, operands
types of operations
endian schemes and bit ordering

26. Course Content Ch. 11 addressing modes instruction formats
assembly language
Pentium and PowerPC examples (Ch 10 & 11)
Pentium and PowerPC examples
will use Virgo in lab
will supplement lecture notes
will include some high-level
language to assembly examples here

27. Course Content
Ch. 12
processor organization, register organization, instruction cycle
instruction pipelining
Pentium example
PowerPC example  
time permitting