1. FeRAM Roadmap S. Kawamura (Japan FEP) Here’s a newcomer… April 2001
FEP & PIDS WG (Japan)
FeRAM Roadmap
Here’s a newcomer…
S. Kawamura (Japan FEP)

2. FeRAM Roadmap
(version 5.0)

3. Assumptions 1 Feature Size:
0.35mm expected to be available in early 2002, 0.25mm in x0.7 every 2-3 year.
Memory Capacity:
Intend to be aggressive to establish FeRAM market. x4 every 2-3 year.

4. Assumptions 2 Cell Size: planar  stack (40% reduction),
2T2C  1T1C (40% reduction).
Switching Charge Qsw:
Constant DVbitline=140mV for sensing.
Qsw=Cbitline x DVbitline.
(Planar)
Storage Node
Ferro. Film
Plate
(Stack)
Plate
Ferro. Film
Storage Node

5. FeRAM vs. DRAM
Giga scale integration will be available with a 3D capacitor.
Capacity (Mb)
Plate
Ferro. Film
Storage Node 3D
1T1C
Year

6. DVbitline Estimation
Based on DRAM roadmap, DVbitline estimated to be 140mV.

7. Qsw and Capacitor Structure
Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.

8. Issues 1 In order to enjoy “The Silence of the (other) RAM’s,”
Reliability comes first to be focused on.
*Ferroelectric materials: Should be stable under thermal budgets.
*Fatigue: Some 1E+15 is required to compete with SRAM and DRAM.

9. Issues 2 Application: Cost:
Limited to small capacity embedded memory. Some “killer applications” should appear to establish FeRAM market.
Cost:
Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.

10. Acknowledgements　
FEP & PIDS WG (Japan) would like to thank many researchers in this field in
Japan:
for the basic information and comments to draw up the roadmap, and
the United States and Europe:
for their useful comments to it .