1. Work in Progress --- Not for Publication PIDS Summary, 4-7-06 Peter M. Zeitzoff US Chair ITWG Meeting Vaals, Netherlands April 6-7, 2005

2. Work in Progress --- Not for Publication p. 2--PIDS meeting, SF ITWG, July 11- 13 Participants Thomas Skotnicki (STMicroelectronics, Europe) Bernd Vollmer (Infineon, Europe) Rob Lander (Philips, Europe) Gosia Jurczak (IMEC, Europe) Kristin De Meyer (IMEC, Europe) Frans Widdersheren (Philips, Europe) Shizuo Sawada (Toshiba, Japan) Toshihiro Sugii (Fujitsu, Japan) Makoto Yoshimi (Soitec, Japan) Jim Hutchby (SRC, United States) Peter Zeitzoff (SEMATECH, United States)

3. Work in Progress --- Not for Publication p. 3--PIDS meeting, SF ITWG, July 11- 13 PIDS Summary NVM –2006 ITRS: cross-check with IRC/FEP tables, do other minor updates –2007 ITRS focus Streamline and clarify requirements tables Bring in selected devices from ERD to potential solutions –4 bits/cell option (2005 ITRS: implemented in 2010, colored red) No change in 2006 ITRS Will be re-evaluated in the 2007 ITRS. DRAM –Survey will be done in 2006 of key DRAM producers to prepare for 2007 ITRS –Tentatively, add SOI DRAM in 2007 ITRS

4. Work in Progress --- Not for Publication p. 4--PIDS meeting, SF ITWG, July 11- 13 PIDS Summary (2) Logic –Timing of high-k, metal gate electrode: significant doubt about feasibilility of projected introduction in 2008 We are considering delaying the introduction of high-k and metal gate electrode in the 2006 ITRS –This would require reworking of the tables for several years beyond 2008 –Scaling tradeoffs, probably including performance, will be required –FEP is involved –We will work with Design on variability and leakage limits. Also, to evaluate impact of multi-core processors on transistor performance requirements –MASTAR device simulation package is being extended by STM to include some system oriented simulations