1. 1 2010 Litho ITRS Update Lithography iTWG July 2010

2. 2 Outline Major Challenges Lithography Potential Solutions Some table updates Summary

3. 3 ITRS Working Group

4. 4 Difficult Challenges > / = 16nm

5. 5

6. 6 Difficult Challenges <16nm

7. 7

8. 8

9. 9

10. 10

11. 11 Proposed Optical / EUV Mask Updates

12. 12 Double Patterning Update

13. 13 Preliminary feedback: No differentiation among different products No mask cost increase by node Write time increase No breakdown on critical and non-critical Need to check published data by TSMC and Intel

14. 14 Summary Lithography solutions for 2010 –45 nm half-pitch - 193 Immersion Single Exposure for DRAM/MPU –Flash using Double Patterning (Spacer) for 32 nm half-pitch Lithography solutions for 2013 –32 nm half-pitch Double patterning or EUV for DRAM/MPU –EUV needed – 16 nm half-pitch for Flash and 22nm DRAM/MPU Double exposure / patterning requires a complex set of parameters when different exposures are used to define single features Mask Complexity for Double patterning Mask Infrastructure for EUV