1. ITRS 2010 Test and Test Equipment – San Francisco, USA Test and Test Equipment July 2010 San Francisco, USA Roger Barth - Micron ITRS Test TWG

2. ITRS 2010 Test and Test Equipment – San Francisco, USA 2 2010 Test Team Akitoshi Nishimura Amit Majumdar Anne Gattiker Atul Goel Bill Price Burnie West Calvin Cheung Chris Portelli-Hale Dave Armstrong Davide Appello Dennis Conti Erik Volkerink Francois-Fabien Ferhani Frank Poehl Gibum Koo Hirofumi Tsuboshita Hiroki Ikeda Hisao Horibe Jeong Ho Cho Jerry Mcbride Sanjiv Taneja Satoru Takeda Sejang Oh Shawn Fetterolf Shoji Iwasaki Stefan Eichenberger Steve Comen Steve Tilden Steven Slupsky Takairo Nagata Takuya Kobayashi Tetsuo Tada Tom Williams Ulrich Schoettmer Wendy Chen Yasuo Sato Yervant Zorian Yi Cai Jody Van Horn John YS Kim Kazumi Hatayama Ken Lanier Ken Taoka Ken-ichi Anzou Khushru Chhor Masaaki Namba Masahiro Kanase Michio Maekawa Mike Bienek Mike Peng Li Mike Rodgers Paul Roddy Peter Maxwell Phil Nigh Prasad Mantri Rene Segers Rob Aitken Roger Barth

3. ITRS 2010 Test and Test Equipment – San Francisco, USA 3 2009 Changes DFT –Test data compression and test time potential solutions identified –Major rewrite completed of the Design Chapter DFT section Test Cost –Test cost survey completed that quantifies industry view –Test parallelism dependency by device type modified based on I/O count Adaptive Test –New chapter section shows necessity for adaptive test to lower cost Prober –Complete redo of prober table to address parallelism and power Probecard –LCD display driver probe added as driver Handler –Added 10-50 Watt handler category Test Sockets –Socket BW limitations on current sockets –New future contacting solutions are required

4. ITRS 2010 Test and Test Equipment – San Francisco, USA 4 2010 Drivers Unchanged Revised New Drop Device trends –Increasing device interface bandwidth and data rates –Increasing device integration (SoC, SiP, MCP, 3D packaging) –Integration of emerging and non-digital CMOS technologies –Device characteristics beyond the deterministic stimulus/response model –Fault Tolerant architectures and protocols –3 Dimensional silicon - multi-die and Multi-layer –Multiple Power modes and Multiple time domains –Complex package electrical and mechanical characteristics Test process complexity –Adaptive test and Feedback data –Concurrent test within a DUT –Maintaining unit level test traceability –Device customization / configuration during the test process –Distributed test to maintain cost scaling

5. ITRS 2010 Test and Test Equipment – San Francisco, USA 5 Drivers Economic Scaling of Test –Physical limits of packaged test parallelism –Test data volume –Managing interface hardware and (test) socket costs –Multiple Insertions and System test –Effective limit for speed difference of HVM ATE versus DUT –Trade-off between the cost of test and the cost of quality Unchanged Revised New Drop

6. ITRS 2010 Test and Test Equipment – San Francisco, USA 6 2010 Difficult Challenges Test for yield learning –Critically essential for fab process and device learning below optical device dimensions Detecting Systemic Defects –Testing for local non-uniformities, not just hard defects –Detecting symptoms and effects of line width variations, finite dopant distributions, systemic process defects Screening for reliability –Effectiveness and Implementation of burn-in, IDDQ, and Vstress testing –Detection of erratic, non deterministic, and intermittent device behavior Unchanged Revised New Drop

7. ITRS 2010 Test and Test Equipment – San Francisco, USA 7 2010 Difficult Challenges Potential yield losses –Tester inaccuracies (timing, voltage, current, temperature control, etc) –Over testing (e.g., delay faults on non-functional paths) –Mechanical damage during the testing process –Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, noise –Some IDDQ-only failures –Faulty repairs of normally repairable circuits –Decisions made on overly aggressive statistical post-processing Unchanged Revised New Drop

8. ITRS 2010 Test and Test Equipment – San Francisco, USA 8 Test Cost Components

9. ITRS 2010 Test and Test Equipment – San Francisco, USA 9 Adaptive Test Modify testing based on analysis of previous results –Real-time –Near-time –Off-line Benefits –Higher Quality –Fast Test Time Reduction –Lower cost –Fast yield learning Requires data infrastructure –Database –Analysis tools Confidence Implementation is evolving –Multiple learning steps –Delaying wont ease task

10. ITRS 2010 Test and Test Equipment – San Francisco, USA 10 Test Parallelism Changes Soc, Low Performance Logic, commodity DRAM and Commodity Flash unchanged

11. ITRS 2010 Test and Test Equipment – San Francisco, USA 11 SoC Changes Fault models pulled in Bridging faults to 2011 Full ATE standardized interface delayed from 2013 to 2015 DFT based defect analysis has slightly extended life

12. ITRS 2010 Test and Test Equipment – San Francisco, USA 12 Memory Changes Data rates pulled in thru 2016

13. ITRS 2010 Test and Test Equipment – San Francisco, USA 13 RF Changes Increase in short term Carrier Frequency for 2010 Limited need for 12 GHz requirements… 20GHz appears to be small volume as compared to other devices…may be lack of developed instrumentation Target is now 60+ GHz (personal networks and SR radar)

14. ITRS 2010 Test and Test Equipment – San Francisco, USA 14 Probing Technology Changes 2011 memory roadmap will separate DRAM and Flash in table Low contact force probing process requirement added to roadmap

15. ITRS 2010 Test and Test Equipment – San Francisco, USA 15 Prober Characteristics Many changes / additions from 2008 tables –Probe card dimensions –Test head weight –Temperature accuracy –450mm wafer support –Chuck leakage –Planarity –Etc. Solutions exist until 2014 2009 2008 DRIVERS Full wafer test Device Power

16. ITRS 2010 Test and Test Equipment – San Francisco, USA 16 3D Devices Multiple die system –Sub-systems designed to operate and be assembled together –Process optimized for contents of each die Logic, DRAM, NVM, Analog –Connection by potentially 1000s of TSVs (Thru Silicon Vias) Design, Interconnect, Assembly and Test, PIDS and FEP problem DFT Requirements –Testability of each die –Vias cannot be probed due to ESD issues –N+ die test methodology a possibility as die added, not recommended –Final 3D Packaged test void

17. ITRS 2010 Test and Test Equipment – San Francisco, USA 17 TSV Test Strategy Strong Recommendations –Cant (and dont) touch the TSVs. Alternative test pads with ESD protection are ok (analog, power, digital) Use Boundary scan test for access –Design independently testable die Cannot require resources from other die for test Need not operate in mission mode –Design low resistance TSVs –TSV geometry and parametrics are not be the critical technology limiter Needs –Thermal considerations needed for scan after stack –Optimal functional / performance / system test –Possible benefit to self Speed Test (SST) thru TSV loop (post stack) Trends –System test / validation much more important in the future with TSVs. The die stack is a system.

18. ITRS 2010 Test and Test Equipment – San Francisco, USA 18 Test Time Reduction Potential Solutions Required test time reduction is driven by SoC Assumes increasing design complexity and transistor count will not increase test time

19. ITRS 2010 Test and Test Equipment – San Francisco, USA 19 DFT Compression Potential Solutions Development is necessary to get very high levels of data compression Demonstrated techniques are just approaching 1000x 100k data compression necessary out in time…no clear path yet!

20. ITRS 2010 Test and Test Equipment – San Francisco, USA 20 High Speed Interfaces Bit bandwidth increasing… Physical limit? Test limit? Test Sockets are not able to support controlled impedance contacts at >15 GT/s Limit? Jitter Test Critical for HS Interfaces

21. ITRS 2010 Test and Test Equipment – San Francisco, USA 21 Summary of 2010 table (trend) Changes Device Trends and Challenges significantly updated Minor adjustments to tables –Test parallelism –SoC –Memory –Probing Technology Refinement of TSV testing strategy