1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 5 Nam Pham Van Speed Optimization

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Some adder structure Slide 2

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design comparison (Synopsys) Slide 3 Condition: Supply voltage 1.2 V All libraries were used (CORE65LPLVT, CORE65LPSVT, CORE65LPHVT)

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Chosen design Slide 4 Han Carlson Adder (a parallel prefix adder): Combination of Brent Kung & Kogge Stone structure One of the faster adder Suitable for VLSI A = 0.5 * n * log(n) T = log 2 (n) + 1

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock How to achieve better speed performance? Slide 5

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock At behavioral / design level Improvement can be done with: Pipelining  higher throughput Array structures Tree structures Replication (parallelization) Combinations of those Slide 6

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Delay investigation - example inverter Slide 7 Low delay T with: Lower capacitance C Higher width W of the transistors (p-transistors 3x bigger than n-transistors)

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Strategy: Layout optimization  C l At the transistor level  ß ( W and L ) Supply voltage  V dd 0 Technology optimization Propagation Delay T : t r : rise time t f : fall time T = (t r + t f ) / 2 C l : capacitance ß : unity gain V dd : supply voltage W : width L : length Slide 8

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Voltage & Libraries comparison (Synopsys) Slide 9 Condition: All libraries (CORE65LPLVT, CORE65LPSVT, CORE65LPHVT) Condition: Supply Voltage 1.3 V

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Chip with pads Power (P dyn / P leak ) 359.6078 mW / 6.2586 mW Metric (J -2 ) [4.07989* 10 21 ] ASIC design – Cadence Encounter Slide 10 Values of ASIC Timing (T min / f max ) 0.33 ns / 3030 MHz Power (P dyn / P leak ) 24.2087 mW / 9.1597 µW # Pipeline Stages8 Metric (J -2 )[4.140*10 25 ] Core size5248 µm 2 Core utilization90 %

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Source 1.Behrooz Parhami; „Computer Arithmetic – Algorithms and Hardware Designs“, University of California 2.Reto Zimmermann; „Binary Adder Architectures for Cell-Based VLSI and their Synthesis“ 3.Prof. Dirk Timmermann; „Systemgerechte Algorithmen“, „Hochintegrierte Systeme I & II“, Universität Rostock Slide 11

12. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 12