ITRS 2000 Update - Taipei, Taiwan, 11/06/00

ITRS 2000 Update - Taipei, Taiwan, 11/06/00
ITRS/ORTC Tables Technology Node, DRAM Chip Size, Logic Chip Size, and key TWG Line-items (“1999 ” refers to 1999 ITRS; “Sc. 2.0” refers to the IRC “Most Aggressive” Scenario 2.0 Proposal, 7/11/00) ITRS 2000 Update Review - Taipei 12/6/00 Rev 1kg_h, 11/7/00 Contact: Alan Allan , ITRS 2000 Update - Taipei, Taiwan, 11/06/00

ITRS Table Definitions/Guidelines, Proposal Rev1, 7/11/00
Technology Requirements Perspective - Near-Term Years : First Yr. Ref.+ 6 yrs F’cast (ex through 2005), annually - Long-Term Years : Following 9 years (ex.: 2008, 2011, and 2014), every 3 years Technology Node : - General indices of technology development. - Approximately 70% of the preceding node, 50% of 2 preceding nodes. - Each step represents the creation of significant technology progress - Example: DRAM half pitches (2000 ITRS) of 180, 130, 90, 65, 45 and 33 nm *Year 2000 : Smallest 1/2 pitch among DRAM, ASIC, MPU, etc Year of Production: - The volume = *10K units (devices)/month. ASICs manufactured by same process technology are granted as same devices - Beginning of manufacturing by *a company and another company starts production within 3 months　　 Technology Requirements Color : - : Manufacturable Solutions are NOT known : Manufacturable Solutions are known : Manufacturable Solutions exist, and they are being optimized *Year 2000 : Red cannot exist in next 3 years (2000, 2001, 2002)** *Year 2000 : Yellow cannot exist in next 1 year (2000) Red Yellow White ** Exception: Solution NOT known, but does not prevent Production manufacturing ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (Technology Node): Technology Node Assumptions (per IRC Proposal 7/11/00): a) DRAM Half-Pitch: 1999: 3-year Node cycle (0.7x/3yrs), except year 2005 shifted off trend Sc.2.0: 130nm pull-in to 2001 and ~.7x/3yrs(.5x/6yrs) reduction rate 1999 (nm): /180, 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; /70, 2011/50, 2014/35 Sc.2.0 (nm): 1999/180, 2000/150, 2001/130, 2002/115, 2003/100, 2004/90, /80; 2008/60, 2011/40, 2014/30 Note: .7x/Node(.5x/2 Nodes): 2001/130; 04/90; 07/65; 10/45; 13/33; 16/23 b) MPU/ASIC Half-Pitch: 1999: MPU/ASIC Half-Pitch Same, lagged typically 1-2 years behind DRAM Sc.2.0: tied to DRAM: pull-in one year starting 160nm in 2001, then ~.7x/3yrs(.5x/6yrs) reduction rate 1999 (nm): /230, 2000/210, 2001/180, 2002/160, 2003/145, 2004/130, 2005/115; /80, 2011/55, 2014/40 Sc.2.0 (nm): 1999/230, 2000/190, 2001/160, 2002/145, 2003/130, 2004/115, /100; 2008/70, 2011/50, 2014/35 ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (Technology Node): Technology Node Assumptions (cont.): c) MPU/ASIC “In Resist” Gate Length: 1999: MPU Gate Length 2-year node cycle (.7x/2yrs) to 2001, then 3-year node cycle (.7x/3yrs); ASIC Gate Length typically lagged ~1 node behind MPU Sc.2.0 : 1. MPU Same as 1999 ITRS, except Variable ranges in 2002, , 2014 replaced by single targets; 2. ASIC same as MPU 1999 (nm): MPU: /140 , 2000/120, 2001/100, 2002/85-90, 2003/80, 2004/70, 2005/65; /45, 2011/30-32, 2014/20-22 ASIC: /180 , 2000/165, 2001/150, 2002/130, 2003/120, 2004/110, 2005/100; /70, 2011/50, 2014/35 Sc.2.0 (nm): MPU/ASIC: 1999/140 , 2000/120, 2001/100, 2002/90, 2003/80, 2004/70, /65; 2008/45, 2011/33, 2014/23 d) NEW (Sc.2.0) (nm): MPU/ASIC “Physical Bottom” Gate Length line item targets added which are pulled-in 1 year from the Lithography “In Resist” targets. NEW (Sc.2.0) (nm): 1999/120, 2000/100, 2001/90, 2002/80, 2003/70, 2004/65, /60; 2008/40, 2011/30, 2014/20 e) Litho TWG Proposal: Full 70% Reduction of Printed Gate Length from Sc.2.0, plus 1-year lead for “Physical Bottom Gate Length” ITRS 2000 Update - Taipei, Taiwan, 11/06/00

=> Roadmap portion still under discussion ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (cont.- DRAM): DRAM Assumptions: a) Cell Area Factor Limits (from FEP TWG): 1999: 8x/1999 -> 6x/2002 -> 4.4x/2005 -> 3.0x/2011 -> 2.5x/2014 Sc.2.0: 8x/ , 6x/ , 4x/ b) Cell Array Efficiency Limit Trends (from FEP, Nikkei Microdevices): 1999: Intro: /70% --> 2016/75% Sc.2.0: Intro: /70% --> 2016/75% 1999: Production 1999/53% --> 2016/57% Sc.2.0: Production 1999/53% --> 2016/58% c) Litho Field Size (from Litho TWG): 1999: 4x Magnification, 6-inch Reticle Intro x32 = 800mm2 Production x32 = 400mm (2 chips/field) Sc.2.0: 5x Magnification, 6-inch Reticle Intro x26 = 572mm2 Production x26 = 286mm2 (2 chips/field) d) Bits/Chip Product Generation Growth Rate: 1999: : 2x bits/chip every 2 years Introduction: Through 8Gbit: 2x bits/chip every 2 years; After 8Gbit: 2x bits/chip every 2-3 years (4x/5years) @ Production: Through 32Gbit: 2x bits/chip every 2 years; After 32Gbit: 2x bits/chip every 2-3 years (4x/5years) ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Summary of Key Assumption Proposed Changes [1999 ITRS vs. Sc.2.0 Proposal] (cont.- Logic): MPU Assumptions: a) High Performance (HP) Starting Chip Size: WAS: 2Mbyte on-chip (6t) SRAM in 1999 (170mm2 Core plus 280mm2 SRAM = 450mm2/1999) IS: 1Mbyte on-chip (6t) SRAM in 1999 (170mm2 Core plus 140mm2 SRAM = 310mm2/1999) b) Cost Performance (CP) Starting Chip Size (SAME as 1999 ITRS): c) SRAM and Logic Transistors/chip Trend (SAME as ITRS) = 2x/2yrs d) Chip Size Growth Rate Trend WAS/ IS: Flat chip sizes through 2001, then 1.2x/4rs ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Chip Size - Model Assumptions, Notes, Tables ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Chip Size - Model Assumptions, Notes, Tables (cont. - MPU) ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Part 2 - DRAM Tables ( Note that target node years for Scenario 2.0 are now proposed to be: /180nm; /130nm; 2004/90nm; /65nm; 2010/45nm; /33nm; 2016/23nm) ITRS 2000 Update - Taipei, Taiwan, 11/06/00

[This Page Left Intentionally Blank] ITRS 2000 Update - Taipei, Taiwan, 11/06/00

DRAM - ORTC Chip Size Model Per IRC Technology Node Proposal [IS, 7/11/00] (cont): ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Part 3 - MPU/ASIC Tables ( Note that target node years for Scenario 2.0 are now proposed to be: /180nm; /130nm; 2004/90nm; /65nm; 2010/45nm; /33nm; 2016/23nm) ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Part 4 - Other ORTC Table TWG Line Items ( Note that target node years for Scenario 2.0 are now proposed to be: /180nm; /130nm; 2004/90nm; /65nm; 2010/45nm; /33nm; 2016/23nm) ITRS 2000 Update - Taipei, Taiwan, 11/06/00

Other ORTC Table TWG Line Items - Table 2a,b Litho Field Size Litho Wafer Size FEP, FI - Table 3a,b # of Chip I/O’s Test, Design # of Package Pins/Balls Test, A&P - Table 4a,b Chip Pad Pitch A&P Cost-Per-Pin A&P Chip Frequency Design Chip-to-Board Frequency A&P Max # Wire Levels Interconnect - Table 5a,b Electrical Defects Def. Reduct. - Table 6a,b P.Supply Volt. PIDs Max. Power Design, PIDs - Table 7a,b Affordable Cost Economic (AA actg) Test Cost Test ITRS 2000 Update - Taipei, Taiwan, 11/06/00

ITRS 2000 Update - Taipei, Taiwan, 11/06/00

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ITRS 2000 Update - Taipei, Taiwan, 11/06/00

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