1. Department of Computer Systems / TKT-1527 1 Design for Testability / O. Vainio 15.9.2015 Motivation  Testability is an important quality metric in electronic systems  Cost of test is beginning to dominate the per-part cost of mant silicon products, e.g., in consumer market  Time-to-market pressures force the need of structured, repeatable and automatic test features as part of overall design methodology  In system-on-chip designs, test data management and cost of test are important  Reusable IP blocks need designed-in test features  Learn terminology  Industrial demand, employment opportunities

2. Department of Computer Systems / TKT-1527 2 Design for Testability / O. Vainio 15.9.2015 Testing and Diagnosis  Testing: the system is exercised and the response is analyzed to check whether it behaved correctly  Diagnosis: if incorrect behavior is detected, locate the cause of misbehavior. - Assumes knowledge of the internal structure of the system

3. Department of Computer Systems / TKT-1527 3 Design for Testability / O. Vainio 15.9.2015 Main Categories of Tests Logic verification or functionality tests - Done before chip tapeout to verify the functionality of the design Silicon debug - Run on the first batch of chips that return from fabrication - Confirm that the chip operates as intended and help debug any discrepancies - Can be done at full speed, more extensive than logic verification tests - Less visibility inside the chip compared to design phase

4. Department of Computer Systems / TKT-1527 4 Design for Testability / O. Vainio 15.9.2015 Main Categories of Tests Manufacturing test or Production test - Done on each manufactured chip before shipping to the customer to verify that the silicon is completely intact - Verify that every transistor, gate, and storage element in the chip functions correctly

5. Department of Computer Systems / TKT-1527 5 Design for Testability / O. Vainio 15.9.2015 Yield  Not all die on a wafer function correctly  There may be bridged connections or missing features due to dust particles, imperfections in materials or photomasking, etc.  Imperfections may result in a fault  Yield is the number of good die divided by the total number of die per wafer  The goal of a manufacturing test procedure is to determine which die are good and should be shipped to customers

6. Department of Computer Systems / TKT-1527 6 Design for Testability / O. Vainio 15.9.2015 Cost of Detecting a Fault Wafer:$0.01 - $0.1 Packaged chip:$0.1 - $1 Board:$1 - $10 System:$10 - $100 Field:$100 - $1000

7. Department of Computer Systems / TKT-1527 7 Design for Testability / O. Vainio 15.9.2015 n Combinational logic Exhaustive testing

8. Department of Computer Systems / TKT-1527 8 Design for Testability / O. Vainio 15.9.2015 n Combinational logic clk m m reg Example: n = 25 m = 50 Test takes 1  s per pattern

9. Department of Computer Systems / TKT-1527 9 Design for Testability / O. Vainio 15.9.2015 Basic Digital Debugging  When a chip returns from fabrication, the first tests are run in a lab environment  Need a circuit board with features to support testing: - Power for the IC with ability to vary V DD and measure power dissipation - Analog and digital inputs and outputs as required - Clock inputs as required - A digital interface to a PC - Zero insertion force socket for the chip

10. Department of Computer Systems / TKT-1527 10 Design for Testability / O. Vainio 15.9.2015  The chip should have a serial UART port or some other interface that can be used independently of the normal operation of the chip  Software should provide for peeking (reading) and poking (writing) registers in the chip  Also an interface for a logic analyzer may be provided

11. Department of Computer Systems / TKT-1527 11 Design for Testability / O. Vainio 15.9.2015 Initial Steps in Chip Testing  ”Smoke test”: ramp up supply voltages from zero without clocks running and monitor the current.  Enable the clocks, some dynamic current should be evident. If possible, initially use reduced clock speed.  Examine various registers using PC-based peek and poke software, checks the integrity of the interface.  The chip may have built-in self test that can be activated over a boundary scan interface.  Otherwise, the functionality is checked from the bottom-up.  Top-level test like running a piece of code at once often does not work, usually because of problems with the test fixture.

12. Department of Computer Systems / TKT-1527 12 Design for Testability / O. Vainio 15.9.2015 Some Pointers for Debugging  Keep a dated logbook for all tests done.  Do one change at a time and observe the result. Changing many things will not logically lead to the bug (”shotgun approach”).  Check everything two or three times; never assume anything unless it is measured and logged in a notebook.  Check signals and supply voltages at the pins of the IC; new test boards may have errors.  Perform continuity checks from the IC pins to expected places  Never count out a possible reason for a bug

13. Department of Computer Systems / TKT-1527 13 Design for Testability / O. Vainio 15.9.2015  Use freeze spray or heat gun to check for temperature problems.  Check the state of any internal registers against documentation.  Evaluate the timing of inputs and outputs with respect to the clock. Setup or hold times may be violated in a new test setup.  When a bug is discovered, hunt for other portions of the design that might have a similar bug.  Never assume anything – question everything.  When the chip is demonstrated to be operational, you can measure more subtle characteristics such as performance.

14. Department of Computer Systems / TKT-1527 14 Design for Testability / O. Vainio 15.9.2015 Testers and Test Fixtures  A tester is a device that can apply a sequence of stimuli to a chip or system under test and monitor and/or record the results  Four general types of test fixtures are: - A probe card to test wafers or unpackaged dies - A load board to test a packaged part - A PCB for bench-level testing (with or without tester) - A PCB with the chip in situ, demonstrating the application for which the chip is used

15. Department of Computer Systems / TKT-1527 15 Design for Testability / O. Vainio 15.9.2015 Handlers  An IC handler feeds ICs to a test fixture attached to a tester.  Devices are gravity-fed to a handler, which mechanically picks the chips up and places them in the test socket on the load board.  The tester stimulus is then applied and chips are binned depending on whether or not they passed the test.

16. Department of Computer Systems / TKT-1527 16 Design for Testability / O. Vainio 15.9.2015 Shmooing  The ability to vary the voltage and timing on a per-pin basis with a tester allows a process called ”Shmooing”.  For instance, vary V DD from 3 V to 6 V while varying the tester cycle time.  A shmoo plot shows the sensitivity of the part with respect to voltage.  Another example of shmoo is to skew the timing on inputs with respect to clock to look for setup and hold variations.

17. Department of Computer Systems / TKT-1527 17 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0****** 1.1***** 1.2**** 1.3*** 1.4** 1.5* 1.01.11.21.31.41.5 voltage Normal, well-behaved shmoo Typical speedpath Clock Period in ns * indicates failure

18. Department of Computer Systems / TKT-1527 18 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0*** 1.1*** 1.2*** 1.3*** 1.4*** 1.5*** 1.01.11.21.31.41.5 voltage ”Brick wall” Bistable initialization Clock Period in ns

19. Department of Computer Systems / TKT-1527 19 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0*** 1.1*** 1.2*** 1.3*** 1.4*** 1.5*** 1.01.11.21.31.41.5 voltage ”Wall” Fails at a certain voltage (coupling, charge sharing, races) Clock Period in ns

20. Department of Computer Systems / TKT-1527 20 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0***** 1.1**** 1.2*** 1.3** 1.4* 1.5* 1.01.11.21.31.41.5 voltage ”Reverse speedpath” Leakage Clock Period in ns

21. Department of Computer Systems / TKT-1527 21 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0 1.1 1.2 1.3 1.4****** 1.5****** 1.01.11.21.31.41.5 voltage ”Floor” Works at high but not low frequency (leakage) Clock Period in ns

22. Department of Computer Systems / TKT-1527 22 Design for Testability / O. Vainio 15.9.2015 Shmoo plot 1.0 1.1 1.2**** 1.3** 1.4 1.5 1.01.11.21.31.41.5 voltage ”Finger” Coupling Clock Period in ns