1. Front End Processes 2010 ITRS
ITRS Public Conference
03 December 2010
Tokyo
2010 FEP ITWG Meeting Participants:
US: J. Barnett, R. Jammy, M. Walden, P. Majhi, T. Pan, L. Chang, G. Celler, M. Goldstein
Japan: M. Watanabe,
Europe: M. Alessandri, Y. Le Tiec
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2. 2010 ITRS FEP Sub-TWG Leadership
HP MPU ASIC - FEP 2
Prashant Majhi (US)
LOP - FEP 3
LSTP - FEP 4
DRAM - FEP 5
Open
Floating Gate Flash - FEP 6
Mauro Alessandri (EU)
Charge Trapping Flash - FEP 7
PCM - FEP 8
FeRAM - FEP 9
Yoshimasa Horii (JP)
Starting Materials - FEP 10
Mike Walden (US)
Mike Goldstein (US)
Surface Preparation - FEP 11
Joel Barnett (US)
Therm/Thin Films/Doping - FEP 12
Prashant Majhi (US)
Etch - FEP 13
Tom Lii (US)
CMP - FEP 14
Darryl Peters (US)

3. 2010 FEP Update Goals Close PIDS-FEP Table inconsistencies
Address Design Vdd Scaling Concerns
Correct DRAM a-Factor in DRAM Table
Incorporate any ORTC Scaling Changes
Update Surface Prep. Potential Solutions
Update CMP Potential Solutions
Update Difficult Challenges

4. 2010 Starting Materials Highlights
Minor correction in analysis area for nanotopography table entry (FEP10) to better reflect industry actual practice (from 2 mm diameter to 2 mm x 2mm analysis area) – related footnote I also corrected
No other changes

5. 2011 Starting Materials Opportunities
Continue to monitor industry activities related to 450mm development and assess impact on the Starting Materials table entries
Several key table items are indicated at 32nm HP and beyond as “Solutions not Known” – these need to be addressed
Revisit adding edge roll-off metric(s) – model development dependent (treat in text if model is not available)
Consider the possible impact to wafer flatness requirements assuming adoption of EUV for lithography
Review progress relative to FinFET potential adoption and revisit “Partially Depleted” silicon starting layer thickness table entries, as appropriate

6. 2010 Surface Prep Update 2010 Updates limited to Potential Solutions
More on Integrated Cleans - Thermal Budget driving needs
Multi level resists considered for resist strip
Advanced material (Ge/ III-V) considerations for PR and particle removal
YE group in agreement that particle models need updating
Obtaining pertinent data extremely difficult
FEP/YE to discuss best approach

7. 2011 Surface Prep Opportunities
Improving outdated metrics
Particles
Identify drivers/modules
Epi a defect magnifier, pre gate metrics same for gate 1st/last
Metals (No longer gate related metrics?)
Pre-EPI now more critical? Sum of all 30 < 1E10
CCD? DRAM?
Consideration of wafer organic, oxygen and moisture specifications for low temp processing
Separate out oxygen as pre-epi and metal (front end vs. BEOL)
Identify where there may be a need controlled environments/FOUPS
Modify material loss specs per appropriate clean
Is current loss spec aggressive enough? Move to 0.1A – reiterate methodology
Incorporate loss specs for Spacer SiN, WF metal, High-k? Metal loss spec for DRAM stacked capacitor.
Measuring loss a metrology issue
Incorporate new materials/architectures – Ge based, III-V, MUG-FinFET
Particles probably the same, material loss different?
Update BEOL tables for cleans
K value shift, CD Loss, bowing, adhesion, particles – steer clear of electrical parameters that aren’t easily measured; suppliers to define, IC houses to approve

8. Thermal/Thin Films/Doping 2010 Update and 2011 Opportunities
No updates in 2010
Identification of deterministic doping requirements and techniques in 2011
Considerations for Ge and III-V processing in 2011
Close discussion with PIDS-ERM to incorporate high mobility channels as solutions for scaling CMOS for high performance at low power.
Include any potential impact of 3D for FEP tables

9. 2010 Etch Update
Etch process technology requirement table updated, table listed below
Recent advanced litho tool greatly improves across chip line width variation to allow same LWR budget between 2010 and 2011
On-etcher metrology will be needed for further reducing lot to lot and wafer to wafer gate CD variation

10. 2011 Etch Opportunities Update etch potential solutions table
LWR becomes largest portion of gate CD variation. Add VUV resist treatment for potential LWR improvement
Include etch induced silicon recess reduction with pulse plasma and new etch chemistry
Include alternative channel material etching development
Add high-K/MG replacement gate integration highly selective gate metal to gate metal etch
Add 3D device highly selective gate etch
Continue improving outdated metrics in etch process technology requirement table

11. HP, LOP, LSTP 2010 Highlights and 2011 Opportunities
Unified Vcc Scaling with PIDS-Design
Revise technology insertion points and re-align timelines for major transitions (planar; ETSOI; finFET and for MUGFET and high mobility channels (Ge, III-V)) in consultation with ERD, PIDS
Working on including high mobility channels into tables for main technology solution with PIDS-ERM
Conducted workshop during VLSI to gather expert opinion
Continue with e-workshop’s with experts to include specific targets for the tables.
Unify certain device specifications [including speed and power] with PIDS (in consultation with Design)
Ion, Ioff, CV/I Roadmap
Understand 3D interconnect impact to device (strain, leakage, parasitic’s, etc) with PIDS
List N and PFET Tables separately

12. Memory (DRAM, Floating Gate Flash, Charge Trapping Flash, PCRAM, FeRAM) 2010 Update and 2011 Opportunities
No updates in 2010
For 2011, consider adding scaling parameters related to the transistors in the array and periphery for DRAM
Incorporate 1 year pull in for DRAM M1 ½ pitch and NAND Flash un-contacted poly ½ pitch
Consider adding requirements for 3D memory architectures (Charge Trapping Flash and DRAM)
Consider adding STT-RAM requirements

13. CMP Plans and Opportunities
No update for 2010
Revise 2009 STI tables and text, where necessary
Review and revise timetable and metrics
Review and revise challenges
Review and revise solutions
Review and revise text
Add section for replacement metal gate
Proposed CMP metrics (poly open polish (POP), and metal polish) to be extracted from literature, ISMI, and Sematech
Time table, text, challenges, and solutions
Define post-CMP cleans requirements
Coordinate with Interconnect TWG
Avoid duplication of effort
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14. 2010 FEP Updates Summary Starting Materials:
Minor correction in analysis area for nanotopography, 2011 activities identified
Surface Prep:
Updated Potential Solutions Table, 2011 activities identified
Thermal/Thin Films/Doping:
No updates, 2011 activities identified
Etch:
Adjust 2011 Line Width Roughness (LWR), 2011 activities identified
Stacked DRAM:
Non-volatile memories
HP/LOP/LSTP
Unified Vcc Scaling with PIDS-Design
Working with PIDS-ERM on including high mobility channels into 2011 tables for main technology solution
Continue with e-workshop’s with experts to include specific targets for the tables.
Revising technology insertion points for MUGFET and high mobility channels (III-V)
Work with PIDS on 3D interconnect impact to device (strain, leakage, parasitic’s, etc)
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