1. Winter Public Conference ORTC 2010 Update
A. Allan, Rev 2, 12/02/10

2. 450mm timing presently unchanged from 2009 ITRS position
IRC 2010 Update Messages:
450mm timing presently unchanged from 2009 ITRS position
However, FI will extend 300mm wafer generation in parallel line item header with 450mm; and
Emphasize compatibility of productivity extensions into the 450mm generation;
FI update also indicates that its activities are relevant to legacy wafer generations (e.g. MtM technologies)
More than Moore white paper final ITWG draft is completed and available online
New “Moore’s Law and More” Graphic update proposal for the 2011 ITRS Executive Summary Renewal
The 2010 ITWG work is based on frozen 2009 Headers
Technology Pacing focus issues identified and addressed (see Technology Pacing agenda Foil)
Beyond CMOS –
Research tools and material (pre-alpha material and tool) timing needs to be taken into account
PIDS and ERD and ERM are coordinating new technology transfers (e.g. InGaAs; Ge) for 2011 ITRS work Kickoff proposals
ESH shifting focus to future material use and risk mitigation (living “white paper” proposed) on ITRS forum site
IRC 2010 Summary special topics
Energy topic Updated
ERD/ERM Next Memory Storage Spring Meeting completed 3rd conference in Japan at Winter meeting
Technology Pacing CTSG proposals are integrated into PIDS Tables and ORTC Table1 at Dec’10 Japan Workshop for the 2011 ITRS Executive Summary Renewal
Equivalent scaling graphic update for the 2011 ITRS Executive Summary Renewal
Parallel bulk and SOI pathways
Clarification of gate mobility materials pathway
Comparison alignment with ITRS dimensional vs. industry typical “node” trends

3. IRC/CTSG Winter 2010 Technology Pacing Cross-TWG Study Group (CTSG) Agenda:
IRC/Technology Pacing CTSG TOPICS - CTSG 2010 Proposals considered
During Winter Meeting 2011 Renewal work from 2H10 CTSG Discussions:
PIDS and FEP Memory Survey Proposal Updates - to be used for 2011 Renewal
FEP and Design and System Drivers – will investigate MPU and Leading Edge Logic technology trend proposals for 2011 Renewal
Plus Continued 1Q11 CTSG 2011 Renewal work on:
Litho – develop proposals utilizing # of Mask layers inputs [see ICKnowledge (ICK) contribution in backup]
Design/Interconnect - Andrew/Juan-Antonio/Chris Case - reconciled the Interconnect and Design Tables alignment issues
A&P/Design - Bill Bottoms/Andrew/Juan-Antonio – work on proposals for reconciling the Power Dissipation (absolute "hot spot" basis rather than total chip area for 2011 Renewal
PIDS/Design – work on 2011 Renewal proposals for
New Max Chip Frequency trends (lower model basis plus long term trend)
Changes to the 13% PIDS Overhead trend vs. new Design Max Chip Frequency trends;
Updates regarding ring-oscillator basis;
Timing changes to “equivalent scaling” tradeoffs with dimensional scaling
ORTC model update proposals added from work in 2H10 CTSG work for 2011 Renewal

4. Figure 4 The Concept of Moore’s Law and More
2010 ITRS Summary Figure 4
Figure 4 The Concept of Moore’s Law and More
More than Moore: Diversification
More Moore: Miniaturization
Combining SoC and SiP: Higher Value Systems
Baseline CMOS: CPU, Memory, Logic
Biochips
Sensors
Actuators HV
Power
Analog/RF
Passives
130nm
90nm
65nm
45nm
32nm
22nm
16 nm . V
Information
Processing
Digital content
System-on-chip
(SoC)
Beyond CMOS
Interacting with people and environment
Non-digital content
System-in-package
(SiP)

5. 2010- Update Flash Poly Definition
2009 Definition of the Half Pitch – New Poly Definition
[No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables]
Source: ITRS - Exec. Summary Fig 1
Poly
Pitch
Typical flash
Un-contacted Poly
FLASH Poly Silicon ½ Pitch
= Flash Poly Pitch/2
8-16 Lines Lines
Metal
Typical DRAM/MPU/ASIC
Metal Bit Line
DRAM ½ Pitch
= DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch
= MPU/ASIC M1 Pitch/2

6. Structure (electrostatic control)
2010 ITRS Summary Figure 3 “Equivalent Scaling” Roadmap
Figure 3 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes”
and ITRS trends for comparison)
Updated Proposal for 2011 work [from 11/11 CTSG; 11/15 IRC telecon]
Metal
High k
Gate-stack material
2009
2012
2015
2018
2021
Bulk
FDSOI
Multi-gate
(on bulk or SOI)
Structure (electrostatic control)
Channel
material
2nd generation
Si + Stress S D
High-µ
InGaAs; Ge; ?
PDSOI
nth generation
Possible
Delay
Possible Pull -in 6
See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)
68nm
45nm
32nm
22nm
16nm
2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nm
MPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm
2009 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm
11nm
2009 IS ITRS Flash Poly :
54nm
2009 ITWG Table Timing:
= Additional timing movement
considerations for 2011 ITRS work

7. 2010 Update ITRS ORTC Technology Trend Pre-Summary
ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other ORTC section features:
“Equivalent Scaling” timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS; however need for continued discussion about transfer of alternative Gate Material technology in 2011 Renewal
Logic “Equivalent Scaling” Roadmap Timing Update underway, and ongoing discussion of alignment of “node” and dimensional Trends for 2011 Renewal
New “More than Moore” (MtM) white paper completed for 2011 ITRS Renewal impact and added to the ITRS website at
MPU contacted M1
Unchanged for 2010 [validated by FEP data]
2-year cycle trend through 2013
Cross-over DRAM M1 2010/45nm
Smaller 60f2 SRAM 6t cell Design Factor
Smaller 175f2 Logic Gate 4t Design Factor
Two proposals [2011 Renewal work]: for Design TWG to evaluate possible 1-year M1 delay (IC TWG: two companies not meeting roadmap); and also evaluate alignment of “nodes” with latest M1 industry status and also High Performance/Low Power timing needs (Taiwan IRC request)
DRAM contacted M1
Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from 2007/08/09 ITRS; new 4f2 Design factor begins 2011
Proposal [2011 Renewal work]: 1-year pull-in of M1 and bits/chip trends to end of roadmap*; 4f2 push out [to 2013]; *no Flattening of DRAM M1 as with Flash Poly**
Flash Un-contacted Poly
Unchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added “equivalent scaling” bit design:
Inserted 3bits/cell MLC ; and delayed 4bits/cell (2 companies in production) until 2012
Proposal #1[2011 Renewal work]: year pull-in of Poly; however slower ~4-year cycle trend to 2015/18nm; then 3-year trend to 2022; ** then Flat Poly after 2022/8nm; and 3bits/cell extended to 2018; 4bits/cell delay to 2019
Additional Proposal consideration underway for 2011 Renewal due to recent announcements

8. 2010 Update ITRS ORTC Technology Trend Pre-Summary (cont.)
5) Unchanged for 2010 Tables: MPU GLpr – ’08-’09 2-yr flat; Low operating and standby line items track changes
Unchanged for 2010 Tables: MPU GLph – ’08-’09 2-yr flat with equiv. scaling process tradeoffs; Low operating and standby line items track changes
Performance targets (speed, power) on track with tradeoffs
7) Primarily Unchanged [corrections to Intro Level product line items – see backup] for 2010 Tables: MPU Functions/Chip and Chip Size Models
Utilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and updated cell design factors
ORTC line item OverHead (OH) area model, includes non-active area
ORTC model impact updating from PIDS/FEP Survey proposals evaluation underway for 2011 Renewal]
DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation “Moore’s Law” doubling cycle;
smaller Chip Sizes (<60mm2) with 4f2 design factor included
Flash Bits/Chip and Chip Size Model Unchanged for 2010 Tables
2-year generation “Moore’s Law” doubling cycle;
growing Chip Sizes after return to 3-year technology cycle
IRC 450mm Position: Pilot lines/2012; Production/ Unchanged for 2010; also Unchanged: “double S-curve” graphic in 2010 Update Summary
450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by ISMI to IRC for 2011 ITRS Renewal preparation
ISMI is pursuing 450mm program activities to meet the ITRS Timing
Evaluation of possible impact of a delayed scenario is underway for 2011 ITRS Renewal preparation

9. Figure 1 ORTC Table 1 with PIDS update proposals for 2011 ITRS effort)
2010 ITRS Summary Figure 1
Figure 1 ORTC Table 1 with PIDS update proposals for 2011 ITRS effort)
[including PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]
Note: additional proposals for 2011 ITRS work are under consideration due to recent additional industry technology implementation acceleration announcements. Updates will be delivered at public meetings in 2011.

10. 2010 ITRS Summary Figure 2
Figure 2 ORTC Table 1 Graphical Trends (including overlay of PIDS update proposals for 2011 ITRS effort)
16nm
Near-Term
Long-Term
PIDS DRAM Projection
~1-yr pull-in
42nm M1 to 2010 (2 co’s);
Then 3-yr cycle to 2024/8nm;
PIDS Flash Projection
~2-yr pull-in
26nm Poly half-pitch to 2010 (2 co’s);
Then ~4-yr cycle to 2020/10nm;
Then 3-year cycle to 2022/8nm;Then flat
2019: PIDS Flash 4 bits/cell push-out
Memory
PIDS 2011
Proposals
2013: PIDS DRAM 4f2 Design Factor bits/cell push-out
Source: ITRS - Executive Summary Fig 7a

11. Figure 5a DRAM and Flash Memory Half Pitch Trends
2010 ITRS Summary Figure 5a
Figure 5a DRAM and Flash Memory Half Pitch Trends
16nm
Near-Term
Long-Term
Source: ITRS - Executive Summary Fig 7a

12. Figure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends
2010 ITRS Summary Figure 5b
Figure 5b MPU/high-performance ASIC Half Pitch and Gate Length Trends
16nm
Near-Term
Long-Term

13. Square Micrometers (um2)
2010 ITRS Summary Figure 6
Figure ITRS Product Function Size Trends: MPU Logic Gate Size (4-transistor); Memory Cell Size [SRAM (6-transistor); Flash (SLC and MLC),
and DRAM (transistor + capacitor)]
2009 ITRS:
Function Size
MPU/ASIC
Alignment
With Latest
Design TWG
Actual SRAM [60f2]
& Logic Gate [175f2]
DRAM
4f2
Added
Beginning
2011
Flash [4f2]
1) 2-yr Cycle
Extended to 2010;
2) 3 bits/cell added ;
3) 4 bits/cell moved
To 2012
Square Micrometers (um2)

14. 2010 ITRS Summary Figure 7a
Figure 7a ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends

15. 2010 ITRS Summary Figure 7b
Figure 7b ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends
2011: “22nm”/(38nm M1)
MPU Model Generations

16. Volume Development Production
2010 ITRS Summary Figure 8
Figure 8 A Typical Wafer Generation Pilot Line and Production “Ramp” Curve applied to Forecast Timing
Targets of the 450 mm Wafer Generation
Volume
Years
Alpha
Tool
Beta
Tools for
Pilot line
32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011
Consortium Pilot Line
Manufacturing
22nm (extendable to 16nm) M1 half-pitch capable tools
Development
Production
450mm 32nm M1 half-pitch
Pilot Line Ramp
2010
2011
2012
2013
2014
2015
2016

17. 2010 Winter Meeting Public Conference Backup
ITRS “S-curves” Ramp Timing definition
ERD/ERM “Beyond CMOS” Definition Graphic
ORTC Table 2D corrections
SICAS Capacity Analysis Graphics 60nm Split-out Analysis Update
Typical Industry “Node” Tracking vs ITRS Technology Trends
Work in Progress – Do Not Publish!

18. Production Ramp-up Model and Technology Cycle Timing
2009 WAS Unchanged
Production Ramp-up Model and Technology/Cycle Timing
Months
-24
Alpha
Tool 12 24
-12
Development
Production
Beta
First
Conf.
Papers
First Two Companies
Reaching Production 2 20
200 2K
20K
200K
Additional
Lead-time:
ERD/ERM
Research and
PIDS Transfer
Volume (Wafers/Month)
Production Ramp-up Model and Technology Cycle Timing
*Examples: 25Kwspm ~=
280mm2
140mm2
100mm2
70mm2
Source: ITRS - Exec. Summary Fig 2a
Work in Progress – Do Not Publish!

19. Work in Progress – Do Not Publish!
ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing
[Example: MOSFET High-mobility Channel Replacement Materials]
Source: ITRS - Executive Summary Fig 2b
Months
Alpha
Tool
Development
Production
Beta
Product
Volume (Wafers/Month) 2 20
200 2K
20K
200K
Research
-72 24
-48
-24
-96
Transfer to PIDS/FEP
(96-72mo
Leadtime)
First
Tech. Conf.
Device Papers
Up to ~12yrs
Prior to Product
2019
2017
2015
2013
2011
2021
Hi-m
Example:
1st 2 Co’s
Reach
Circuits Papers
Up to ~ 5yrs
2009 WAS Unchanged
Work in Progress – Do Not Publish! 19

20. 2008 ITRS “Beyond CMOS” Definition Graphic
[2009 – Unchanged]
2008 ITRS “Beyond CMOS” Definition Graphic
Computing and Data Storage Beyond CMOS
Source: Emerging Research Device Working Group
“More Moore”
“Beyond CMOS”
22nm
16nm
11nm
8nm
Baseline
CMOS
Ultimately
Scaled CMOS
Functionally
Enhanced CMOS
Spin Logic
Devices
Nanowire
Electronics
Ferromagnetic
Logic Devices
32nm
Channel Replacement Materials
Low Dimensional Materials Channels
Multiple gate MOSFETs
New State Variable
New Data Representation
New Devices
New Data Processing
Algorithms
Work in Progress – Do Not Publish!

21. Work in Progress – Do Not Publish!
ORTC Table 2D - Including Corrections
Work in Progress – Do Not Publish!

22. Work in Progress – Do Not Publish!
ORTC Table 2C - Including Corrections
Work in Progress – Do Not Publish!

23. 4Q09 SICAS Update Proposal Work in Progress – Do Not Publish!
From Furukawa-san/Japan
To IRC 3/28/10 (modified by AA)
Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution
>0.7mm mm mm mm mm mm
<0.08mm mm
<0.06mm
Feature Size (Half Pitch) (mm)
= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual
= 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target
= 2009 ITRS Flash Un-contacted Poly Half Pitch Target
= 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target
3-Year Cycle
2008/09 ITRS: 2.5-Year Ave Cycle for DRAM
3-Year Cycle
After 2010 for
Flash; after 2013
For MPU
2-Year DRAM Cycle
3-Year DRAM Cycle ; 2-year Cycle Flash and MPU
Year
Year
2010
2013
* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. 
The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that range
of the feature size (y-axis). Data are based upon capacity if fully utilized.
Source: ITRS - Executive Summary Fig 3
Work in Progress – Do Not Publish!

24. Industry “Node”* Alignment w/ITRS [2009 ITRS]
MPU Perform/Power “Equiv. Scaling”:
Copper
Strain
HiK/MG I, II
FDSOI
MUGFET; SiGE
Hi-u tbd
TBD
DRAM Density “Equiv. Scaling”:
8f2
6f2
4f2
Flash Density MLC “Equiv. Scaling”:
16/11/8/5.5/4f2: 2b/cell
2.0f2: 2b/cell
1.5f2: 3b/cell
1.0f2:4b/cell
Dimensional Half Pitch Scaling (EOT not shown):
2009 ITRS:
Past  Future
2.5
7.5
‘17
‘16
‘18
‘20
‘19
‘21
‘25
‘23
‘22
‘24
‘10
‘08
‘06
‘04
‘02
‘12
‘00
‘14
‘11
‘13
‘99
‘01
‘03
‘05
‘07
‘09
‘15
Year
Hi-Performance
MPU/hpASIC
Public Node
References*;
+extrapolation 54
~Actual 76
107
151
214 38 27 21
303 64 90
127
180 32 24 19
255 45
“Node”
“65”
“90”
“130”
“45”
“180”
“32”
“22”
“16”
->
“8.0”
“5.6”
“4.0”
“11”
“28”
“40”
“55”
“80”
“110”
“160”
“20” 52
DRAM Actual M1 68 90
119
157 40 32 25
207 59 78
103
136 36 28 22
180 45 16 11 8 38
Flash Actual Poly 54 76
107
151 28 22 18
207 45 64 90
127 25 20 16
180 32 11 8 6
’01-’03: 200mm->300mm
@ 180nm->130nm M1
’14-’16: 300mm->450mm
@ 32nm->22nm M1
’91-’93: <200mm ->200mm
@ 0.5u->0.35u M1
Industry Typical “Node” vs ITRS M1 and Poly Alignment
2009 ITWG Table Timing: ]
68nm
45nm
32nm
22nm
16nm
2009 IS ITRS DRAM M1 :
2009 ITRS MPU/hpASIC M1 : nm 65nm 54nm 45nm 38nm 32nm 27nm nm nm
MPU/hpASIC “Node*”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”
2009 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm
2009 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm
11nm
2009 IS ITRS Flash Poly :
54nm
2) hpASIC reference TSMC “Nodes” Articles: ;
1) MPU reference: Mark Bohr Tutorial, Jul’09:
*Notes on “Nodes”: DRAM, Flash “Nodes” ~= M1 and Poly Half-pitch.
However high performance Logic (MPU, hpASIC) may have node “labels” Associated with their dimensional technology progress, as referenced in:
MPU & ASIC Low-Power versions typically lag Gate Length to manage power and performance trade-offs at the same M1-based density “Node” as high-performance versions