1. Metrology Roadmap 2001 Update EuropeAlain Deleporte (ST) Ulrich Mantz (Infineon) Vincent Vachellerie (ST) Vincent Vachellerie (ST)JapanKorea Taiwan Henry Ma (EPISIL) USJames Whetstone (NIST) Alain Diebold (Int. SEMATECH)

2. AGENDA 1999 – 2000 - 2001 2001 Difficult Challenges 2001 Technology Requirements 2001 Potential Solutions

3. 1999 Metrology Roadmap Highlights

4. Metrology Challenges by 2000 ITRS Node Timing Brings RED Closer

5. New to – Five Difficult Challenges 65nm / Before 2007 New to – Five Difficult Challenges 65nm / Before 2007 Key requirement for Cu/Damascene metrology is void detection in Cu lines and pore size distribution (find killer voids) Scribe line shrinkage reduce test structure area making high precision measurements difficult in scribe lines.

6. Determination of manufacturing Metrology when device and interconnect technology remain undefined. New to – Five Difficult Challenges 65nm / After 2007 New to – Five Difficult Challenges 65nm / After 2007

7. Difficult Challenges

9. Metrology Challenges by 2001 ITRS Node Timing Brings RED Closer

10. FEP TWG Requests to Metrology Make sure Clive is at May 17 FEP meeting Important feature is channel length at silicon interface which is etched gate length FEP introducing new roadmaps for FERAM and Flash –Need metrology to know if FERAM is fatigued –Metrology for inter-poly dielectric Need to close on the metrology info in the starting materials section of FEP Discuss EOT models which seem to have issues below 1 nm - Curt to write Discuss need to make software more user friendly and not use lookup tables Multiple high k layers are being developed as potential high k and optical models need to be developed. Nano-laminate of Al and Hf oxide How do you achieve statistical significance using non-goal post methods, I.e., range of defects. Metrology measurements need to comprehend In-line monitoring for epi-growth

11. Factory Integration TWG and Metrology Define Integrated Metrology Stand alone unit more capable than integrated metrology Includes Cluster tool and sensor based measurements. Process level, Wafer level, tool level metrology Near term Metrology community would benefit from factory integration modeling factory modeling to determine factory impact. Metrology community looks to working with the factory integration community to develop Standards for open architecture to allow IC manufacturer to select metrology

12. Metrology TWG Requests Interconnect TWG –2001 Requirements Tables –Barrier Thickness –Insulator Killer Pore Size and conc. –Cu line Void conc. or %

13. Interconnect TWG Requests to Metrology Voids in Cu and low k pore size metrology Add discussion on Cu ECD bath metrology See new planarization requirements such as metric for thinning of dielectric For SOC –K value of high k at high frequency –R and L measurements needs (thick metal thickness, composition) Etch –Sidewall angle –Trench bottom profile, possibly after planarization –Diagnostic for run to run stability –End point for low k etch –In-situ monitoring and process control feedback –High aspect ratio contact etch Bottom CD Profile and angle End point detection

14. Litho TWG Requests to Metrology TWG Add Line Edge roughness requirements –Kyle Patterson correlated line edge roughness on electrical properties at SPIE 2001 Registration of Mask after pellicle placement Measurement of Arc n, k, thickness need specs Measure minimum dimension (height and width) of scattering and anti scattering bars Overlay kerf structures do not represent on chip variation Litho will separate optical and non optical NGL mask requirements. Some will deal with metrology. Are there unique metrology requirements that need to be addressed.

15. Packaging TWG Requests to Metrology TWG 4 new sections: Opto-electronics, MEMS, multi-chip, materials Metrology areas : –Need good input parameters for Thermal Mechanical Simulation Interfacial adhesion Bulk vs microstructural properties –Nano-indentation not broadly available –Need to understand fracture toughness thus need to measure modulus variation during use and test. –Scanning acoustic microscopy, x-ray, and adhesion are now in- line for packaging –Laser Moire are becoming in-line for stress measurement –High frequency materials properties

16. Why are CD Measurement Requirements RED? There is no universal metrology solution for all CD measurements. –e.g., Scatterometry meets Focus-Exposure precision needs to (70 nm node?) for resist lines but not for contacts (yet). 3D info needed for undercut gate, contact, and other structures. Precision includes tool matching and near + long term measurement variation.

17. CD-SEM a Potential Solution for Wafer and Mask / R&D + Production From Sato and Mizuno, EIPBN 2000, Palm Springs, CA Barriers and Solutions 193 & 157 nm Resist Damage » lower dose images Precision Improvements » new nano-tip source Depth of Focus » new SEM concept needed Ultimate Limit of CD-SEM » ~ 5 nm for etched poly Si Gate

18. 60nmnode130 / 90nmnode 40nmnode Schottky Emitter Anode Final Aperature Detector Magnetic Lens Electrostatic Lens Specimen Z U col U E CD-SEM Depth of Focus vs Resolution Damage to 193 Resist from e beam & DoF Structure Coherent Electron Beam illumination footprint detector e holography Boot Tip Line Scan CD-AFM Tip technology low throughput Tip Technology scatterometry Metal Gates 0th order Incident Laser Beam contacts CD Potential Solutions for Mask and Wafer

19. Reason for Red is Precision and Tool Matching IR or UV for In-Line ? Existing in-line metrology 60nmnode 130 / 90nmnode 40nmnode Gate Dielectric Metrology Potential Solutions Enable High k Development with Existing Tool

20. Interconnect Metrology Solutions Barrier/Seed Cu Films 5 Potential Solutions all expected to meet precision requirements some are extendable to patterned wafers Acoustic ISTS Picosecond acoustics X-ray reflectivity X-ray fluorescence Non-contact resistivity

21. Materials Characterization Enables Process and Metrology Development Oxynitride and High k Interfaces Dave Muller - Lucent NRA Total N in oxynitride

22. Metrology & New Structures Gate Drain Source Vertical Transistor

23. 2000 and 2001 Changes Accelerated Timeline Brings RED closer……….. Developments in some CD measurements push Red out further for some applications?