1. Research Summary and Schedule m5151117 Yumiko Kimezawa August 1, 20121RPS

2. Outline Summary -Minor change of BANSMOM system -Adding Ethernet Sub-system to BANSMOM System -Understanding Ethernet Standard Design Schedule August 1, 2012RPS2

3. Minor Change of BANSMOM System Investigation of BANSMOM System -Need to divide Master CPU memory into inst. mem and data mem -Need to use off-chip memory August 1, 2012RPS3 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Master CPU Memory Master CPU Memory Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA DMA controlle r ECG Data ECG Data

4. August 1, 2012RPS4 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Data Mem Data Mem Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA DMA controlle r ECG Data ECG Data Inst Mem Investigation of BANSMOM System -Need to divide Master CPU memory into inst. mem and data mem -Need to use off-chip memory Minor Change of BANSMOM System

5. August 1, 2012RPS5 : Data flow : Control signal : Data flow : Control signal Graphic LCD Controller Data Mem Data Mem Master CPU Timer Graphic LCD Graphic LCD LED JTAG UART JTAG UART PPD Module Master Module LED Controller LED Controller Avalon Bus FIR Filter Timer Slave CPU Memory Slave CPU External Memory External Memory Shared Memory Shared Memory FPGA DMA controlle r ECG Data ECG Data Inst Mem Investigation of BANSMOM System -Need to divide Master CPU memory into inst. mem and data mem -Need to use off-chip memory Minor Change of BANSMOM System

6. August 1, 2012RPS6 Minor Change of BANSMOM System SOPC Builder Display

7. Adding Ethernet Sub-system to BANSMOM System Ethernet sub-system This system is not compiled. August 1, 20127RPS

8. Understanding Ethernet Standard Design August 1, 2012RPS8 Fig: Block Diagram of Standard Design Example I added Ethernet sub- system to BANSMOM system but compiling of it was not successful I’m constructing Ethernet standard design like a fig. to understand why compiling was not successful -I’m not done yet -I’m still assigning pin

9. Schedule August 1, 2012RPS9 Aug. Sept. Nov. Oct. Dec. Compete hardware part -Ethernet -DMA controller Compete software part Test and evaluation Finish writing master thesis

10. August 1, 2012RPS10

11. Block Diagram of Standard Design Example August 1, 2012RPS11 System Timer High-Resolution Timer Performance Counter JTAG UART Push-Button PIOs LED PIOs Pipeline Bridge DDRx System ID Nios II CFI Flash Tristage Controller Tristage Conduit Bridge Pipeline Bridge Performance Counter JTAG UART Push-Button PIOs LED PIOs Peripheral Sub-System Ethernet Sub-System

12. sgdma Memory to memory August 1, 2012RPS12