1. ITRS - YE ITWG Conference in HsinChu December 5, 2012 Lothar Pfitzner

2. Scope of Yield Enhancement
Aspects
Manufacturing of integrated semiconductor devices: numerous processing steps building the 3D structure of the chip (e.g. 9 Cu and low –k interconnect layers for 32 nm)
Yield: percentage of operating chips at the end of the manufacturing process
Components
Determination and control of contamination
Inspection of structures and critical dimensions
Model to predict and calculate yield based on historic contamination levels (particulate and metals) and defects (failures)
Determination of kill ratios: Correlation between defects and yield
A bird’s-eye view of 0.128µm2 FinFET SRAM cells (post silicide formation)
Toschiba,
45 nm ramp production was the fastest
Presented by Mark Bohr (Intel) 02/2009
Gordon Moore: “There is no fundamental obstacle to achieving device yields of 100%.” (Electronics, 38 (8), 1965)

3. Example: Inspection for ‘More than Moore’
Applications
‘More Moore’
and
‘More than Moore’ technologies
power electronics
mechatronics
MEMS applications
packaging and assembly
3 D integration
Laboratory scale inspection setup fulfilling requirements of low cost components and large area inspection (4 mm *4 mm field of view at µm resolution) (example for 3D integration, EC & BMBF funded project JEMSIP3D under contract ENIAC Call 2008 / )
Test layout routing lines (CEA Leti)

4. Contamination Analysis for Manufacturing Control
Drivers
ultra clean manufacturing
unintended contamination of layers
dimensional, structural and compositional information
depth resolved quantification
non-volatile organic surface contamination
Analytical Techniques for Manufacturing Control
x-ray metrology
GCMS
TBD
HEPA Filter for contamination free manufacturing (source wikipedia)
For metals, Grazing Incidence X-Ray Fluorescence (GIXRF) could be a possible solution providing dimensional quantification and qualification of surface near elemental contamination.
Elemental depth profiling with GIXRF
Elemental analysis of contamination with TXRF

5. Objectives of Yield Enhancement
collect defect data
tools for inspection and root cause analysis
automated defect classification and filtering
inspection strategy
yield management
software
objective: to correlate data and find excursions
predict yield
defect data excursions
define specs
procedure for clarification
process
module 1
process
module 2
process
module k k 2 1
wafer
wafer
wafer
manufacturing
defect
densities
inspection and collection of data
defect
classification
review, characterization, metrology

6. Defects and Failure Mechanisms
processes: litho, etch thin film implantation, planarization, cleaning,…
faults and problems: defects as e.g. particles, flatness, layer properties, patterns, dimensions
challenges
yield and defect map in 2 D
root cause analysis requires 3 D
requires fast and non-destructive inspection (defect density) and metrology (root cause analysis) for 2D and 3D structures  CIA
requires preventive defect and contamination control  WECC
model, predict and forecast yield
ESD Damage
Interconnects
overlay
crack
Metal 2
Via
particle
open
short
Metal 1
particle
layer thickness p+ n n+ p p
COP
n-well
p-well
contamination
interfaces: roughness, state density, charges
Si crystal: stacking faults, contamination, stress, COP (crystal originating particles), epi defects

7. Organization of the Chapter 2012
Chair: Lothar Pfitzner (Fraunhofer IISB) Co-Chair: Dilip Patel (ISMI)
Difficult Challenges
Table YE 2
Technology Requirements and Potential Solutions
Wafer Environment Contamination Control (WECC)
Chair: Kevin Pate (Intel) – USA, Andreas Neuber (AMAT) - Europe
Table YE 3, YE 4, YE 4a
Characterization, Inspection & Analysis (CIA)
Co-Chair: H. Nagaishi and I. Thurner – Europe
Table, YE 5, YE 6, YE 7
Yield Learning (YL – not active in 2012)
Chair: N.N.; Contributor defined by AMAT
Yield Model and Defect Budget (YMDB – not active in 2011 and 2012)
Chair: N.N.

8. 2012 YE ITWG Contributors (please update)
Europe
Lothar Pfitzner ( chair, Fraunhofer IISB )
Andreas Neuber ( WECC, AMAT )
Sabrina Anger (CIA, Fraunhofer IISB)
Yannick Borde ( WECC, ST Crolles )
Jan Cavelaars ( CIA, NXP )
Arnaud Favre ( WECC, Adixen )
Giuseppe Fazio ( Micron )
Francois Finck ( CIA, ST )
Astrid Gettel ( WECC, GLOBALFOUNDRIES )
Mathias Haeuser ( CIA, Infineon )
Fontaine Herve (CEA)
Christoph Hocke ( WECC, Infineon Technologies
Francesca Illuzzi ( WECC, Micron )
Hans Jansen ( WECC, ASML )
Jost Kames ( WECC, artemis control AG )
Barry Kennedy ( CIA, Intel )
Jens Mueller (MWGroup)
Andreas Nutsch ( CIA, PTB)
Dieter Rathei ( CIA, DR Yield )
Ines Thurner ( CIA, CONVANIT )
Hubert Winzig ( WECC, Infineon )
Japan
Yoshimi Shiramizu ( WECC, co-chair, Renesas )
Takashi Futatsuki ( WECC, Organo )
Teruyuki Hayashi ( WECC, TEL )
Masahiko Ikeno ( CIA, Hitachi High-Technologies )
Katsunobu Kitami ( WECC, Kurita )
Kaoru Kondoh ( WECC, Rion )
Naoki Kotani (CIA, Panasonic )
Sumio Kuwabara (CIA, STARC)
Yasuhiko Matsumoto ( WECC, Rohm )
Fumio Mizuno ( WECC, MEISEI University )
Hiroshi Nagaishi ( CIA, Renesas )
Kazuo Nishihagi ( WECC, HORIBA )
Koichiro Saga ( WECC, SONY )
Isamu Sugiyama ( WECC, NOMURA )
Makiko Tamaoki (Toshiba)
Yoshitaka Tatsumoto ( CIA, Lasertec )
Hiroshi Tomita ( WECC, Toshiba )
Takahiro Tsuchiya ( CIA, Fujitsu semiconductor )
Ken Tsugane ( WECC, HITACHI )
Korea
Young Jeong Kim ( Samsung)
United States
Scott Anderson ( ,, Balazs-AirLiquide )
Dwight Beal ( WECC, PMS )
David Blackford ( WECC, Fluid Measurement Technologies )
Dilip Patel ( YE co-chair, ISMI )
Marc Camenzind ( WECC, Balazs-AirLiquide )
Jeff Chapman ( WECC, IBM )
John DeGenova ( WECC, Texas Instruments )
Dan Fuchs ( WECC, Air Liquide)
Rick Godec ( WECC, Ionics Instruments )
Barry Gotlinsky ( WECC, Pall )
Jeff Hanson ( WECC, Texas Instruments )
Keith Kerwin ( WECC, TI )
Suhas Ketkar ( WECC, APCI )
John Kurowski ( WECC, IBM )
Bob Latimer ( WECC, Hach )
Slava Libman ( WECC, Air Liquide - Balazs Nanoanalysis )
Chris Muller ( WECC, Purafil, Inc. )
Kevin Pate ( WECC, Intel )
Larry Rabellino ( WECC, SAES )
Rich Riley ( WECC, Intel )
David Roberts ( WECC, Nantero )
Biswanath Roy ( WECC, Pall )
Tony Schleisman ( WECC, Air Liquide )
Drew Sinha ( WECC, Siltronic )
Terry Stange ( WECC, Hach Ultra Analytics )
Dan Wilcox ( WECC, Replipoint Technologies )
Milton Goldwin ( CIA, ISMI )
Charley Dobson ( WECC, TI )
Asad Haider ( WECC, TI )
Ruben Pessina ( WECC, TI )
William Moore ( WECC, IBM )
Rushikesh Matkar ( WECC, Intel )
Ravi Laxman ( WECC, Air Liquide )
Hubert Chu ( WECC, AMAT )
Robert Clark ( WECC, TEL )
Singapore
Guillaume Gallet ( WECC, Camfil)
Paul Tan WECC)
Taiwan
Wai-Ming Choi ( Entegris)
Ychuang Huang (TSMC)
Victor Liang (TSMC)
Ray Yang (UMC)
Mao-Hsiang Yen (Winbond)
Thank you
very much!
Status 12/2012

9. 2013 Key Challenges Near Term (2013-2018)
The Yield Enhancement community is challenged by the following topics:
Near Term ( )
Detection and Identification of Small Yield Limiting Defects from Nuisance - It is a challenge to detect multiple killer defects and to differentiate them simultaneously at high capture rates, low cost of ownership and high throughput. Furthermore, it is a dare to identify yield relevant defects under a vast amount of nuisance and false defects.
Process Stability vs. Absolute Contamination Level – This includes the correlation to yield test structures, methods and data that are needed for correlating defects caused by wafer environment and handling to yield. This requires determination of control limits for gases, chemicals, air, precursors, ultrapure water and substrate surface cleanliness.
Detection of organic contamination on surfaces – The detection and speciation of nonvolatile organics on surfaces is currently not possible in the fab. There is no laboratory scale instrumentation available.

10. 2013 Key Challenges
The Yield Enhancement community is challenged by the following topics:
Long Term ( )
Next Generation Inspection - As bright field detection in the far-field loses its ability to discriminate defects of interest, it has become necessary to explore new alternative technologies that can meet inspection requirements beyond 13 nm node. Several techniques should be given consideration as potential candidates for inspection: high speed scanning probe microscopy, near-field scanning optical microscopy, interferometry, scanning capacitance microscopy and e-beam. This assessment should include each technique’s ultimate resolution, throughput and potential interactions with samples (contamination, or degree of mechanical damage) as key success criteria.
In - line Defect Characterization and Analysis – Based on the need to work on smaller defect sizes and feature characterization, alternatives to optical systems and Energy Dispersive X-ray Spectroscopy systems are required for high throughput in-line characterization and analysis for defects smaller than feature sizes. The data volume to be analyzed is drastically increasing, therefore demanding for new methods for data interpretation and to ensure quality.
Next generation lithography - Manufacturing faces several choices of lithography technologies in the long term, which all pose different challenges with regard to yield enhancement, defect and contamination control.

11. Overall YE activities Activities performed since Summer Meeting:
Review and update of tables
Summary text for Executive Overview
 2012 revision of the YE ITRS roadmap chapter completed by September 2012
(Details concerning revisions are presented by the following slides)
Future Fab International Article “Yield Enhancement”
Update of membership list

12. WECC: Liquid Chemicals/ Ultra Pure Water/ Gases/Precursors
Recent activities:
Review and update of Table YE 3 “Technology Requirements for WECC”
Review and update of Figure YE 3 “Potential Solutions for WECC”
Ongoing/ planned activities:
Continue and expand FMEA for metals, anions, and organics
Improve particle deposition models
Update CVD/ALD precursor tables

13. WECC: AMC Recent activities: Ongoing/ planned activities:
Introduction of two new tables in the latest ITRS roadmap version:
Table YE 4 “AMC monitoring methods”
Table YE 4a “Supporting table for on-line methods”
Review and text update of WECC and AMC chapter
YE 3 clarification on refractory limits and footnote explanations introduced
Ongoing/ planned activities:
Definition/standardization of „organics“
Review for „AMC Definition“
Introduction of EUV related contamination
Discussion to add bare wafer suppliers requirements
Review of „Potential solutions”
Adjustments of the AMC limits
Introduction of moisture as new chemical contamination for description of reticle environment
Identification of critical steps for moisture control in FOUP environment
Review requirements for 450 mm manufacturing

14. CIA – Activities and Messages
Recent activities:
Revision of tables: No changes in
YE4 (now YE5) “Defect Inspection on Pattern Wafer Technology Requirements”,
YE5 (now YE6) “Defect Inspection on Unpatterned Wafers: Macro and Bevel Inspection Technology Requirements”
YE6 (now YE 7) “Defect Review and Automated Defects Classification Technology Requirements”.
Ongoing/ planned activities:
Building upon the basis of the previous „Defect Detection and Characterization“ chapter, the current scope of the chapter was defined in 2011 and confirmed during the meetings of 2010/2011/2012 as facing the characterization, inspection and analysis demands in broad applications (e.g. in the area of ‘More Moore’ and ‘More than Moore’ technologies, power electronics, mechatronics, MEMS applications, packaging and assembly):
A further extension of the scope towards a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics is under discussion. Respective ideas were first discussed during the summer meeting 2012.
 Proposal of Japan concerning extension of CIA focus
Preparation of tables and potential solutions for the revision in 2013 needs further input of demands and intensified discussions w.r.t. their required contents.
Include a new table on metal and organic contamination on wafer surfaces, bevel and edge, and backside.
Include in potential solutions issues of small area detection of organics and metal contamination on wafer surfaces.
Restructure of YE to be proposed by and discussed with the Japanese.

15. Proposal of Japan concerning extension of CIA focus
What to do?
Establish a better balance of defect/contamination detection and fault diagnostics/ control of electrical characteristics in CIA focus
Include statistical/ systematic approach into YE activities
Include device/ chip/ system level tables and requirements into ITRS2013 YE chapter
Why?
Extra/ Missing materials are root cause of yield excursion
 Physical inspection often requires intensive efforts
 Such faults are more easily approached by detection of abnormal device behaviour/ chip malfunction manifesting itself in out-of-spec electrical parameters

16. Proposed example of classification for CIA methodologies
Current focus of CIA chapter:
physical defect detection on wafer (including particle/ contamination)
Shrink of devices  lack of accordant measurement capacity
Objective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation

17. Proposed example of classification for CIA methodologies
Acquisition of electrical characteristics of devices in general faster than acquisition of values of the physical layer
Objective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation

18. Proposed example of classification for CIA methodologies
Characteristics of chip layer: Pass/ Fail
Short test time for one pattern (compared to measurement of electrical characteristics), Fault diagnosis recognizes device defect
Objective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation

19. Proposed example of classification for CIA methodologies
Allows investigation of possible dependencies between data and prediction of yield or electrical characteristics
Objective of CIA: Identification of critical extra/ missing materials based on integration of physical, electrical, functional or statistical observation

20. Outlook Development/ Improvement of the Yield Enhancement chapter
Discussion of the focus of YE chapter
What are the pros and cons of referring to not only physical/process defects but also to device defects and abnormal electrical characteristics of a device?
Does a change of emphasis in YE (CIA) activities make sense (e.g. with respect to the advent of MtM, inclusion of back end Yield, 450 mm technology)?
What about including an improved combination of yield of products/fault diagnosis/control of electrical characteristics and defect/contamination detection of the wafer with the respective statistics in YE activities in order to achieve reasonable yield enhancement?
Should we include tables for virtual metrology and for advanced control strategies?
Reflection of current status and future requirements needs subsequent adjustment of outline and content of the chapter
Keep tables for Front End Processing updated
Add Back End Yield Enhancement specifications
Look into Assembly and Packaging yield enhancement
Determine the requirements w.r.t. yield enhancement for manufacturing of
More Moore
More than Moore 3D
Larger diameter substrates
Masks