1. International Technology Roadmap for Semiconductors 2001
Toshitaka Fukushima, Ph.D
Fujitsu

2. World Semiconductor Council
Transition of ITRS
US Domestic
International
1991
Micro Tech 2000
Workshop Report
2001 ITRS
1992NTRS
2000 ITRS
Update
1994NTRS
1999 ITRS
1997NTRS
1998 ITRS
Update
1998
World Semiconductor Council

3. Mission of ITRS IRC ITWG Technology Needs TWG Potential Solutions
Policy
Goal
Schedule
Coordination
among ITWGs
Coordination
among
Associations
TWG
ESIA
Technology Needs
Potential Solutions in
near & long terms
JEITA
（STRJ)
etc
KSIA
FEP
SIA
ITWG
Test
Design
TSIA

4. Scope of ITRS IRC Crosscut ITWGs Focus ITWG Environment Yield
Safety &
Health
Yield
Enhancement
Modeling & Simulation
Metrology
Design
Test
Front End Processes
Interconnect
Focus ITWG
Lithography
Process Integration
Assembly & Packaging
Factory Integration

5. Composition of ITRS Members
Others
(Design / Assembly / Test)
ESIA (Europe) 8%
Research Inst. /
College, Univ./
National lab. /
Consortia 4%
SIA (US)
38%
JEITA (Japan)
27%
22%
Device
Makers
54%
Equipment /
Materials
Suppliers
KSIA (S.Korea)
20%
TSIA (Taiwan) 8%
19%

6. Chapters of ITRS 2001 Glossary ORTC
12 ITWGs : Design to Modeling & Simulation
- Scope
- Difficult Challenges
- Technology Requirement
- Potential Solutions
System Drivers
Difficult Challenges
Grand Challenges
Introduction

7. Technology Node Timing
Development
Production
10M
Year of Production 1M
Volume of Production (Parts/Month)
Alpha
Tool
Beta
Tool
Production
Tool
100K
10K
Conf.
Papers
Top-Runner Company
Production Followed by Succeeding Companies within Three Months 1K
-24
-12
Months 12 24

8. Technology Node vs. Actual Wafer Production10
W.P.C.
(Total Worldwide Wafer Production Capacity ( Relative Value)
Year
>0.7 um
<0.4 1
Year 2000
>0.8 um
<0.18
Technology Node (um)
0.1
ITRS Technology Node
0.01
1995
2000
2005
Sources:
1995 to 1999: SICAS, 2000: Yano Research Institute& SIRIJ
Year
Year

9. Technology Node 2001 ITRS 1999 ITRS 130 130 100 130 x 0.7 91 90 70 x
(nm)
130
130
100
130 x
0.7 91 90 70 x 90
0.7 64 65 50 x 65
0.7 45 45 35 x 45
0.7 31 32 25 x 32
0.7 22 22

10. Half Pitch
Metal
Pitch
Poly
Pitch
DRAM
MPU/ASIC

11. FEP Grand Challenges Near Term (2001-2007) Long Term (2008-2016)
Gate Stack
Capacitor
Stack / Trench
Source / Drain
- Extension
Isolation
Channel
Contacts
Wells
Starting Material
Near Term ( )
Enhancing Performance
■ 　New Gate Stack and Materials :
● Oxynitride gate dielectric / high performance MOSFETs
● High k gate stack / low operating and low standby power MOSFETs
■ 　CMOS Integration of New Memory Materials and Processes :
● High k DRAM capacitor
● MIM capacitor structures
Long Term ( )
Cost-effective Manufacturing
■ 　Starting Materials alternate beyond 300 mm :
● Productivity enhancement　　● e.g., 450 mm

12. Interconnect Grand Challenges
Near Term ( )
Enhancing Performance
■　Introduction of New Materials :
● High Conductivity and Low k Dielectric
■ 　Integration of New Processes and
Structures :
● High Complexity
Long Term ( )
■ Identify Solutions which address Global
Wiring Scaling:
● Beyond Copper and Low k
● Material Innovation to accelerate Design,
Package and Interconnect

13. Assembly & PKG Grand Challenges
Near Term ( )
Cost-effective Manufacturing
■ Coordinated Design Tools and
Simulators :
● Mix Signal Co-design and Simulation
● Transient Thermal Analysis Tool
● Thermal Mechanical Analysis Tool
● Electrical Analysis Tool
－Power Disturbs
－EMI
－High Frequency / Current and
Lower Voltage Switching
Chip
Package
QFP
BGA
PGA
Printed Wiring Board

14. System Drivers Chapter
1999 ITRS
　■　Major concerns are DRAM, MPU and ASIC though SOC and AMS (analog /
mixed-signa) are slightly mentioned
　■　Each devices are assumed to be developed synchronously along the technology
node.
2001 ITRS
　■　Instead, the Market demands different Technology / Development Timing
depending on the Product Line;
　■Technology Development Trends per Market Segment are analized
(1) Portable and Wireless (2) Broadband
(3) Internet Switching (4) Mass Storage
(5) Consumer (6) Computer
(7) Automotive
　■Technology / Development Timing Demands by Market Segment are extracted
(a) SOC : Multi-technology, High performance, Low cost, Low power
(b) AMS : Low-noise amplifier, Power amplifier, VCO, ADC
(c) MPU : high-volume custom

15. Emerging Research Devices Section
1999 ITRS
　■　Beyond CMOS / Novel Devices
2001 ITRS
　■　Technologies to accelerate the performance on the extension of
classical Roadmap
・ Non-Classical CMOS
　 ・ New memory device
　■　New Technology and Concept beyond classical Roadmap
・ New logic device
・ New architecture

16. Emerging Research Technologies Single/Few Electron Memories
Non-Classical CMOS Tr
ULTRA-THIN BODY SOI
BAND-ENGINEERED Tr
VERTICAL Tr
Fin FET
DOUBLE-GATE Tr
＜Near Future＞
Memory Devices n +
memory node
Engineered barrier Si
Gate
WORD
BIT W R
Magnetic RAM
~2004
Phase Change Memory
~2004
DRAM
2002
Nano Floating Gate Memory >2005
Single/Few Electron Memories
>2007
Molecular Memories
>2010

17. FeRAM Capacitor Structure DRAM FeRAM Planar Stack 3D 64G 512M Plate
Storage Node
Ferro. Film
FeRAM
Plate
S. Node
S. Node
Plug
Plug 1M
Planar
Stack 3D
2000
2005
2010
2015
2020

18. DRAM, MPU/ASIC Half Pitch
1000
DRAM ½ Pitch
MPU/ASIC ½ Pitch
2-year Cycle
150nm
2-year Cycle
90nm
Technology Node - DRAM Half-Pitch (nm)
100
130nm
3-year Cycle
22nm 10
1995
1998
2001
2004
2007
2010
2013
2016
Year of Production

19. LP-ASIC : 2 years behind to MPU
MPU Gate Length
1000
MPU Printed Gate Length
MPU Physical Gate Length
LP-ASIC : 2 years behind to MPU
90nm
Technology Node - DRAM Half-Pitch (nm)
100
45nm
2-year Cycle
65nm
3-year Cycle
（2005
@ITRS’99）
32nm
13nm
9nm 10
1995
1998
2001
2004
2007
2010
2013
2016
Year of Production

20. Gate Dielectrics / EOT nm (High-k)
■ MPU / HP-ASIC in 2007
■ High-k needs to be introduced for LSTP ASIC in 2005:
Ig<1pA/um, EOT=1.8nm

21. Effective Dielectric Constant (Low-k)

22. Lithography ６５nm Node (NGL) Resist Mask CD Control
■　Push Optical Lithography to its Limits :
６５nm Node 　
● Requires very tight Control
Resist
Mask CD Control
■　 Introduction of Next Generation Lithography
(NGL)
　●　 Requires New Infrastructure
　●　 Could’nt reach the Consensus ; in a state of Chaos

23. Lithography Potential Solutions
Node nm
KrF(248nm)
ArF(193nm)
NGL
157nm
EUV(13nm)
EPL
ML2
IPL
PEL
PXL

24. Design / Test / Assembly & PKG
　●　Design Cost Model added
- Rapid Increasement of Design Cost threatens the future
■　Test
　●　Reliability Evaluation added
- A lot of difficulties pointed out in ITRS99 eliminated by DFT
- Development of New Method for acceleration of Potential
Defects needed urgently
■　Assembly and Packaging
　●　 Scope expanded
- ＭＥＭＳ, Optoelectronics, Discrete (Passive Component)
- Passive Component embeded PCB

25. FI / YE ■ Factory Integration ● Scope expanded Wafer Mfg. Chip Mfg.
FEOL
BEOL
Chip Mfg.
Probe/Test
Singulation
Product Mfg.
Packaging
Test
1999 ITRS
2001 ITRS
■　Yield Enhancement (former Defect Reduction)
　●　 Scope expanded
Defect Detection and Characterization
Yield Learning

26. Summary
■　System Drivers Chapter
Technologyn Development Trends per Market Segment are analized
Technology / Development Timing Demands by Market Segment are extracted
■　Emerging Research Devices Section
Non-Classical CMOS, new memory device, new logic device and new architecture
are proposed
■　DRAM half pitch
3-year Cycle Scaling after 2001(90nm in 2004, 65nm in 2007, 32nm in 2010)
■　MPU / ASIC-HP half pitch
2-year Cycle Scaling until 2004, then 3-year Cycle Scaling
■　MPU / ASIC-HP Gate Length
2-year Cycle Scaling until LP-ASIC is 2 years behind to MPU
■　High-k
Introduction is needed in 2005 for LSTP-ASIC, in 2007 for MPU / HP-ASIC
■　Low-k: decelerated
■　 Push Optical Lithography to its Limits
No consensus was reached