1. International Technology Roadmap for Semiconductors
2008 ITRS Update ORTC
[ Konigswinter Germany ITRS ITWG Plenary]
A.Allan, Rev 2,
[notes on IRC/CTSG More Moore, More than Moore, Beyond CMOS 04/04/08]

2. Preliminary Comments
“..the future ain’t what it used to be..” – Yogi Berra
“..the more things change, the more they remain the same..” – Jean-Baptiste Alphonse Karr
“..for everything there is a time..” – Solomon
“..I want what I want when I want it..” – the Customer
“..the customer is king..” – the Seller

3. 2008 Update Definition of the Half Pitch
[No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables]
Poly
Pitch
Typical flash
Un-contacted Poly
FLASH Poly Silicon ½ Pitch
= Flash Poly Pitch/2
8-16 Lines
Metal
Typical DRAM/MPU/ASIC
Metal Bit Line
DRAM ½ Pitch
= DRAM Metal Pitch/2
MPU/ASIC M1 ½ Pitch
= MPU/ASIC M1 Pitch/2
Source: ITRS - Exec. Summary Fig 2
Unchanged

4. Fig 3 Production Ramp-up Model and Technology Cycle Timing -24 12 24
Volume (Parts/Month) 1K
10K
100K
Months
-24 1M
10M
100M
Alpha
Tool 12 24
-12
Development
Production
Beta
First
Conf.
Papers
First Two Companies
Reaching Production
Volume (Wafers/Month) 2 20
200 2K
20K
200K
Source: ITRS - Exec. Summary Fig 3
Fig 3
Unchanged

5. Agenda Pre-Summary MPU Gate Length Technology Trends Update Summary
Backup
Frequency
Bohr URL
SICAS

6. ORTC Pre-Summary – 2008 Update
Flash Model un-contacted poly half-pitch trend
Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;
Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.
Inui-san report:
No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018
NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies
Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]
DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then
Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25);
DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;
Only years affected in 2008 Table Update.
Unchanged
MPU Model M1 stagger-contact half-pitch unchanged from 2007
2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
MPU/ASIC Printed Gate Length Updated
Unchanged 3-year cycle through 2018,
then 3.8-year cycle*
MPU/ASIC High-Performance Physical Gate Length
3.8-year cycle* beginning 2007.
Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios
Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need updated transistor and design model alignment by PIDS, FEP, and Design.
New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and provide ORTC line items.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

7. ORTC Pre-Summary – 2008 Update (cont.)
MPU/ASIC Low Operating Power Printed Gate Length
Two-year delay 2007 from High Performance; one-year delay ; and no delay
MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]
No Change 2007, 2008; two-year delay from High Performance; one-year delay in 2012; and no delay
Also, one decimal place rounding was added to all ORTC 1a,b from
New 2008 “Moore’s Law and More” Working Groups and Definitions Work :
“More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008
More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip
“Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”
The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest ITRS timeframe
Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS
Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.

11. ORTC Summary – 2008 Update
Flash Model un-contacted poly half-pitch trend
Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;
Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip
PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.
Inui-san report:
No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018
NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies
Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]
DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then
Unchanged 3-year cycle* beginning 2010/45nm (2016/22.5; 2022/11.25);
DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;
Only years affected in 2008 Table Update.
Unchanged
MPU Model M1 stagger-contact half-pitch unchanged from 2007
2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
MPU/ASIC Printed Gate Length Updated
Unchanged 3-year cycle through 2018,
then 3.8-year cycle*
MPU/ASIC High-Performance Physical Gate Length
3.8-year cycle* beginning 2007.
Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios
Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need updated transistor and design model alignment by PIDS, FEP, and Design.
New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and provide ORTC line items.
* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]

12. ORTC Summary – 2008 Update (cont.)
MPU/ASIC Low Operating Power Printed Gate Length
Two-year delay 2007 from High Performance; one-year delay ; and no delay
MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]
No Change 2007, 2008; two-year delay from High Performance; one-year delay in 2012; and no delay
Also, one decimal place rounding was added to all ORTC 1a,b from
New 2008 “Moore’s Law and More” Working Groups and Definitions Work :
“More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008
More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip
“Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”
The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest ITRS timeframe
Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS
Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.

13. ORTC Pre-Summary – 2008 Update (cont.)
More than Moore Study Group 4/3/08
ORTC Pre-Summary – 2008 Update (cont.)
More than Moore [discussion leader – Mart Graef also see Backup for additional MtM presentation information]
Objective: Define and quantify value-adding parameters for functional diversification
Identify/elaborate Technical Parameters
Added Value to the target application
Usual ITRS goals: Grand Challenges, Potential Solutions, narrowing over time
Pitfall(Design TWG comment): line item doesn’t “fit”
May need to “tweak” to “fit” the MtM taxonomy
Key parameters for MtM examples in marketplace
Involve IRC/ITWGs
A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs
Key Categories to address: Sensors, Actuators (MEMS, Optical)
Key Issue differentiating “MtM”: Integration
Next Meeting will be called by Mart Graef
TWGs notify Mart of their participant at the April ITRS meeting

14. ORTC Pre-Summary – 2008 Update (cont.)
More than Moore Study Group 4/3/08
ORTC Pre-Summary – 2008 Update (cont.)
Design TWG Proposed “More Moore” and “MtM” Text, 3 apr 2008 Plenary v2a [discussion leader – Andrew Kahng]
1 = More Moore
1a = geometric scaling
1b = equivalent scaling
1c = Design equivalent scaling
NEED: quantifiable, specific Design Technologies that deal with More Moore
“Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”
“Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”
Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional Diversification)
2 = More than Moore
NEED: Design technologies to enable functional diversification
“Design technologies enable new functionality that takes advantage of More than Moore technologies.”
“Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.” 14

15. ORTC Summary – 2008 Update
MPU/ASIC High-Performance Physical Gate Length [discussion leader – A.Allan]
3.8-year cycle* beginning 2007.
Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios
Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) - need updated transistor and design model alignment by PIDS, FEP, and Design.
New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and provide ORTC line items.
Thomas Scotnicki review of Paper and VLSI presentation (see Scotnicki files)
Discrepancy between measured vs ITRS model
Andrew Kahng review – what interconnect capacitance assumed (~zero in ring oscillators)
Proposal for 3 changes to
17% not needed, 8% is enough (due to increased 1 core to 2 core architecture performance)
Variability not taken into account (no manufacturing flexibility) PIDS recommendation
MASTAR Random Generator
Variability vs Device Structure
Not a model problem/limitation – need decision
Not supporting 1/Ion; Want CV/I
Paolo Gargini Review of “Equivalent Scaling Knobs” for Performance/Power tradeoffs
Smaller changes on 5 “knobs” (including Strain, Hik/MetGate, etc) vs historical 2 knobs (Oxide Thickness, Gate Length)
More complex modeling options using Mobility, Dielectric Constant, Voltage “indicators”
“equivalent channel length” possible approach
Andrew Kahng – please advise how to share the investment in manufacturing solutions (“knobs”)?
Beyond CMOS [discussion leader – Jim Hutchby]
“new switch” (asterick “information processing” including interconnect and memory);
Logic switch -> SIA/NRI “invent the new switch”
Graphics need a new color
ERD/ERM (Jim Hutchby, Mike Garner); PIDS (Kwok Ng, Thomas Skotnicki); Design (Andrew Kahng; Juan-Antonio Carballo)
More Moore Study Group 4/3/08
Beyond CMOS Study Group 4/3/08

16. Backup - On-chip Frequency Update Bohr “Tutorial” URL
More than Moore Study Group Kickoff presentation
SICAS 3Q/4Q07 Update

18. Mark Bohr "Silicon Technology Tutorial" :
….Etc.

19. ITRS Spring Meeting 2008 Königswinter, Germany, Rev 1 [Mart Graef]
MtM Study
Group 4/3/08
More than Moore
ITRS Spring Meeting 2008
Königswinter, Germany, Rev 1
[Mart Graef]

20. Functional Diversification (More than Moore)
MtM Study
Group 4/3/08
Functional Diversification (More than Moore)
Scaling (More Moore)
Continuing SoC and SIP: Higher Value Systems
Source: ITRS Document online at:

21. 2007 ITRS “Moore’s Law and More” Definition Graphic Proposal
MtM Study
Group 4/3/08
2007 ITRS “Moore’s Law and More” Definition Graphic Proposal
Computing &
Data Storage
Heterogeneous Integration
System on Chip (SOC) and System In Package (SIP)
Sense, interact,
Empower
Baseline
CMOS
Memory RF HV
Power
Passives
Sensors,
Actuators
Bio-chips,
Fluidics
“More Moore”
“More than Moore”
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)

22. “More Moore” and “More than Moore”
MtM Study
Group 4/3/08
“More Moore” and “More than Moore”
“More Moore”: Scaling Continued shrinking of physical feature sizes of the digital functionalities (logic and memory storage) in order to improve density (cost per function reduction) and performance (speed, power).
“More than Moore”: Functional Diversification Incorporation into devices of functionalities that do not necessarily scale according to "Moore's Law“, but provide additional value in different ways. The "More-than-Moore" approach allows for the non-digital functionalities to migrate from the system board-level into the package (SiP) or onto the chip (SoC). 
The Challenge: Integration of MM with MtM Creation of intelligent compact systems.

23. MtM Study Group 4/3/08
Following Moore’s Law is one approach: Monolithic CMOS logic System-on-Chip
Processor
Radio
Advantage:
Smallest footprint
Disadvantage:
Limited functionality
Storage
Power
Sensor
Actuator
More Moore

24. MtM Study Group 4/3/08
Adding More-than-Moore is another: System-on-Chip and System-in-Package
Processor
Radio
Advantage:
Full functionality
Disadvantage:
Complex supply chain
Storage
Power
Sensor
Actuator
More Moore
More than Moore

25. Proposal for MtM Study Group
Objective: Define and quantify value-adding parameters for functional diversification
Identify/elaborate Technical Parameters
Added Value to the target application
Usual ITRS goals: Grand Challenges, Potential Solutions, narrowing over time
Pitfall(Design): line item doesn’t “fit”
May need to “tweak” to “fit” the MtM taxonomy
Key parameters for MtM examples in marketplace
Involve IRC/ITWGs
A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs
Key Categories to address: Sensors, Actuators (MEMS, Optical)
Key Issue differentiating “MtM”: Integration
Next Meeting will be called by Mart Graef
TWGs notify Mart of their participant at the April ITRS meeting

26. Design TWG Proposed MTM Text, 3 apr 2008 Plenary v2a
More Moore Study Group 4/3/08
1 = More Moore
1a = geometric scaling
1b = equivalent scaling
1c = Design equivalent scaling
NEED: quantifiable, specific Design Technologies that deal with More Moore
“Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”
“Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”
Request: Please remove “b) Multi-core MPU architecture” from 2 (MTM Functional Diversification)
2 = More than Moore
NEED: Design technologies to enable functional diversification
“Design technologies enable new functionality that takes advantage of More than Moore technologies.”
“Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.” 26

27. SICAS Update (www.sia-online.org )

28. SICAS Update (www.sia-online.org )