1. 2009 Litho ITRS Update
Lithography iTWG
July 2009

2. Outline
Lithography Potential Solutions
Major Challenges

3. ITRS Working Group United States Japan Taiwan
Greg Hughes SEMATECH (Chairs)
Mike Lercel IBM
Japan
Takayuki Uchiyama NEC (Chair)
Naoya Hayashi DNP
Masomi Kameyama Nikon
Tetsuo Yamaguchi NuFlare
Taiwan
Anthony Yen TSMC (Chair)

4. Potential Solutions 2009

5. Preferred Technology by Year
2008 SEMATECH Litho Forum survey results
45nm HP
32nm HP
22nm HP

6. 2009 Litho Requirements

7. 2009 Litho Requirements
Single Litho Tool Overlay

8. 2009 Litho Requirements
Restricted Definition of CD - one direction, single pitch, single iso dense ratio.

9. 2009 Lithography Techniques

10. Difficult Challenges > 22nm

11. Difficult Challenges > 22nm

12. Difficult Challenges <= 22nm

13. Difficult Challenges <= 22nm

14. Summary Lithography solutions for 2010 Lithography solutions for 2013
45 nm half-pitch CoO is Driving 193 Immersion Single Exposure for DRAM/MPU
Flash using Double Patterning (Spacer) for 32 nm half-pitch
Lithography solutions for 2013
32 nm half-pitch Double patterning or EUV for DRAM/MPU
22 nm half-pitch Double patterning or EUV for Flash
Double exposure / patterning requires a complex set of parameters when different exposures are used to define single features
LER and CD Control Still remain as a Dominant Issue
Mask Complexity for Double patterning
Mask Infrastructure for EUV